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Kanishka Lahiri: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Kanishka Lahiri, Sujit Dey, Debashis Panigrahi, Anand Raghunathan
    Battery-Driven System Design: A New Frontier in Low Power Design. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:261-267 [Conf]
  2. Kanishka Lahiri, Anand Raghunathan
    Power analysis of system-level on-chip communication architectures. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2004, pp:236-241 [Conf]
  3. Kanishka Lahiri, Anand Raghunathan, Sujit Dey
    Fast system-level power profiling for battery-efficient system design. [Citation Graph (0, 0)][DBLP]
    CODES, 2002, pp:157-162 [Conf]
  4. Kanishka Lahiri, Sujit Dey, Anand Raghunathan
    Communication architecture based power management for battery efficient system design. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:691-696 [Conf]
  5. Kanishka Lahiri, Anand Raghunathan, Ganesh Lakshminarayana
    LOTTERYBUS: A New High-Performance Communication Architecture for System-on-Chip Designs. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:15-20 [Conf]
  6. Kanishka Lahiri, Anand Raghunathan, Ganesh Lakshminarayana, Sujit Dey
    Communication architecture tuners: a methodology for the design of high-performance communication architectures for systems-on-chips. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:513-518 [Conf]
  7. Bren Mochocki, Kanishka Lahiri, Srihari Cadambi, Xiaobo Sharon Hu
    Signature-based workload estimation for mobile 3D graphics. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:592-597 [Conf]
  8. Krishna Sekar, Kanishka Lahiri, Anand Raghunathan, Sujit Dey
    FLEXBUS: a high-performance system-on-chip communication architecture with a dynamically configurable topology. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:571-574 [Conf]
  9. Bren Mochocki, Kanishka Lahiri, Srihari Cadambi
    Power analysis of mobile 3D graphics. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:502-507 [Conf]
  10. Krishna Sekar, Kanishka Lahiri, Anand Raghunathan, Sujit Dey
    Integrated data relocation and bus reconfiguration for adaptive system-on-chip platforms. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:728-733 [Conf]
  11. Phillip Stanley-Marbell, Kanishka Lahiri, Anand Raghunathan
    Adaptive data placement in an embedded multiprocessor thread library. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:698-699 [Conf]
  12. Abhishek Mitra, Marcello Lajolo, Kanishka Lahiri
    SOFTENIT: a methodology for boosting the software content of system-on-chip designs. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2005, pp:361-366 [Conf]
  13. Kanishka Lahiri, Anand Raghunathan, Sujit Dey
    Efficient Exploration of the SoC Communication Architecture Design Space. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:424-430 [Conf]
  14. Kanishka Lahiri, Anand Raghunathan, Sujit Dey
    Fast performance analysis of bus-based system-on-chip communication architectures. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:566-573 [Conf]
  15. Krishna Sekar, Kanishka Lahiri, Sujit Dey
    Dynamic Platform Management for Configurable Platform-Based System-on-Chips. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:641-649 [Conf]
  16. Saumya Chandra, Kanishka Lahiri, Anand Raghunathan, Sujit Dey
    Considering process variations during system-level power analysis. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2006, pp:342-345 [Conf]
  17. Nikhil Bansal, Kanishka Lahiri, Anand Raghunathan, Srimat T. Chakradhar
    Power Monitors: A Framework for System-Level Power Estimation Using Heterogeneous Power Models. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:579-585 [Conf]
  18. Kanishka Lahiri, Sujit Dey, Anand Raghunathan
    Performance Analysis of Systems with Multi-Channel Communication Architectures. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:530-537 [Conf]
  19. Kanishka Lahiri, Sujit Dey, Anand Raghunathan
    Evaluation of the Traffic-Performance Characteristics of System-on-Chip Communication Architectures. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:29-35 [Conf]
  20. Kanishka Lahiri, Anand Raghunathan, Sujit Dey, Debashis Panigrahi
    Embedded Tutorial: Battery-Driven System Design: A New Frontier in Low Power Design. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:261-267 [Conf]
  21. Debashis Panigrahi, Sujit Dey, Ramesh R. Rao, Kanishka Lahiri, Carla-Fabiana Chiasserini, Anand Raghunathan
    Battery Life Estimation of Mobile Embedded Systems. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:57-63 [Conf]
  22. Krishna Sekar, Kanishka Lahiri, Sujit Dey
    Configurable Platforms With Dynamic Platform Management: An Efficient Alternative to Application-Specific System-on-Chips. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:307-0 [Conf]
  23. Nikhil Bansal, Kanishka Lahiri, Anand Raghunathan
    Automatic Power Modeling of Infrastructure IP for System-on-Chip Power Analysis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:513-520 [Conf]
  24. Nikil Dutt, Kaustav Banerjee, Luca Benini, Kanishka Lahiri, Sudeep Pasricha
    Tutorial 5: SoC Communication Architectures: Technology, Current Practice, Research, and Trends. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:8- [Conf]
  25. Kanishka Lahiri, Sujit Dey, Anand Raghunathan
    Communication-Based Power Management. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2002, v:19, n:4, pp:118-130 [Journal]
  26. Kanishka Lahiri, Anand Raghunathan, Sujit Dey
    System-level performance analysis for designing on-chipcommunication architectures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:6, pp:768-783 [Journal]
  27. Kanishka Lahiri, Anand Raghunathan, Sujit Dey
    Efficient power profiling for battery-driven embedded system design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:6, pp:919-932 [Journal]
  28. Kanishka Lahiri, Anand Raghunathan, Sujit Dey
    Design space exploration for optimizing on-chip communication architectures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:6, pp:952-961 [Journal]
  29. Kanishka Lahiri, Anand Raghunathan, Ganesh Lakshminarayana, Sujit Dey
    Design of high-performance system-on-chips using communication architecture tuners. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:5, pp:620-636 [Journal]
  30. Kanishka Lahiri, Anand Raghunathan, Ganesh Lakshminarayana
    The LOTTERYBUS on-chip communication architecture. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:6, pp:596-608 [Journal]
  31. Mohammad Ali Ghodrat, Kanishka Lahiri, Anand Raghunathan
    Accelerating System-on-Chip Power Analysis Using Hybrid Power Estimation. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:883-886 [Conf]
  32. Saumya Chandra, Kanishka Lahiri, Anand Raghunathan, Sujit Dey
    System-on-Chip Power Management Considering Leakage Power Variations. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:877-882 [Conf]

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