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Marcello Lajolo: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Marcello Lajolo, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli
    Fast Instruction Cache Simulation Strategies in a Hardware/Software Co-Design Environment. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1999, pp:347-0 [Conf]
  2. Jie Liu, Marcello Lajolo, Alberto L. Sangiovanni-Vincentelli
    Software timing analysis using HW/SW cosimulation and instruction set simulator. [Citation Graph (0, 0)][DBLP]
    CODES, 1998, pp:65-69 [Conf]
  3. Marcello Lajolo, Luciano Lavagno, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante
    Automatic test bench generation for simulation-based validation. [Citation Graph (0, 0)][DBLP]
    CODES, 2000, pp:136-140 [Conf]
  4. Marcello Lajolo, Mihai Lazarescu, Alberto L. Sangiovanni-Vincentelli
    A compilation-based software estimation scheme for hardware/software co-simulation. [Citation Graph (0, 0)][DBLP]
    CODES, 1999, pp:85-89 [Conf]
  5. Marcello Lajolo, Anand Raghunathan, Sujit Dey, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli
    A case study on modeling shared memory access effects during performance analysis of HW/SW systems. [Citation Graph (0, 0)][DBLP]
    CODES, 1998, pp:117-121 [Conf]
  6. Marcello Lajolo, Anand Raghunathan, Sujit Dey, Luciano Lavagno
    Efficient Power Co-Estimation Techniques for System-on-Chip Design. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:27-34 [Conf]
  7. Marcello Lajolo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante, Luciano Lavagno
    Evaluating System Dependability in a Co-Design Framework. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:586-590 [Conf]
  8. Sathish Chandra, Francesco Regazzoni, Marcello Lajolo
    Hardware/software partitioning of operating systems: a behavioral synthesis approach. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:324-329 [Conf]
  9. Abhishek Mitra, Marcello Lajolo, Kanishka Lahiri
    SOFTENIT: a methodology for boosting the software content of system-on-chip designs. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2005, pp:361-366 [Conf]
  10. Marcello Lajolo, Luciano Lavagno, Matteo Sonza Reorda, Massimo Violante
    Early Power Estimation for System-on-Chip Designs. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2000, pp:108-117 [Conf]
  11. Chen He, Marcello Lajolo, Margarida F. Jacome
    A Case Study of a System Level Approach to Exploration of Queuing Management Schemes for Input Queue Packet Switches. [Citation Graph (0, 0)][DBLP]
    PDP, 2003, pp:401-408 [Conf]
  12. Marcello Lajolo, Matteo Sonza Reorda, Massimo Violante
    Early Evaluation Of Bus Interconnects Dependability For System-On-Chip Designs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:371-0 [Conf]
  13. André C. Nácul, Francesco Regazzoni, Marcello Lajolo
    Hardware scheduling support in SMP architectures. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:642-647 [Conf]
  14. Marcello Lajolo
    Bus guardians: an effective solution for online detection and correction of faults affecting system-on-chip buses. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:6, pp:974-982 [Journal]
  15. Marcello Lajolo, Anand Raghunathan, Sujit Dey, Luciano Lavagno
    Cosimulation-based power estimation for system-on-chip design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:3, pp:253-266 [Journal]

  16. Variation tolerant NoC design by means of self-calibrating links. [Citation Graph (, )][DBLP]


  17. C-based Design of a Flexible Wrapper for Tiled Networks On Chip. [Citation Graph (, )][DBLP]


  18. Automatic synthesis of the Hardware/Software Interface. [Citation Graph (, )][DBLP]


  19. Interface-Centric Abstraction Level for Rapid HW/SW Integration. [Citation Graph (, )][DBLP]


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