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Chein-Wei Jen: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Kun-Bin Lee, Nelson Yen-Chung Chang, Hao-Yun Chin, Hui-Cheng Hsu, Chein-Wei Jen
    A bandwidth and memory efficient MPEG-4 shape encoder. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:525-526 [Conf]
  2. Shih-Hao Ou, Tay-Jyi Lin, Chao-Wei Huang, Yu-Ting Kuo, Chie-Min Chao, Chih-Wei Liu, Chein-Wei Jen
    A 52mW 1200MIPS compact DSP for multi-core media SoC. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:118-119 [Conf]
  3. Tay-Jyi Lin, Chie-Min Chao, Chia-Hsien Liu, Pi-Chen Hsiao, Shin-Kai Chen, Li-Chun Lin, Chih-Wei Liu, Chein-Wei Jen
    A unified processor architecture for RISC & VLIW DSP. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2005, pp:50-55 [Conf]
  4. Tay-Jyi Lin, Hung-Yueh Lin, Chie-Min Chao, Chih-Wei Liu, Chein-Wei Jen
    A compact DSP core with static floating-point unit & its microcode generation. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2004, pp:57-60 [Conf]
  5. Jen-Chien Tuan, Chein-Wei Jen
    An Architecture of Full-Search Block Matching for Minimum Memory Bandwidth Requirement. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1998, pp:152-156 [Conf]
  6. Yuan-Chung Lee, Chein-Wei Jen
    On-Line Polygon Refining Using a Low Computation Subdivision Algorithm. [Citation Graph (0, 0)][DBLP]
    GMP, 2000, pp:209-219 [Conf]
  7. Tay-Jyi Lin, Chin-Chi Chang, Chen-Chia Lee, Chein-Wei Jen
    An Efficient VLIW DSP Architecture for Baseband Processing. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:307-312 [Conf]
  8. Hun-Chen Chen, Jiun-In Guo, Chein-Wei Jen
    A memory efficient realization of cyclic convolution and its application to discrete cosine transform. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2003, pp:33-36 [Conf]
  9. Jiun-In Guo, Chi-Min Liu, Chein-Wei Jen
    A CORDIC-based VLSI Array for Computing 2-D Discrete Hartley Transform. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1571-1574 [Conf]
  10. Jiun-In Guo, Chi-Min Liu, Chein-Wei Jen
    A General Approach to Design VLSI Arrays for the Multi-dimensional Discrete Hartley Transform. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:235-238 [Conf]
  11. Wei-Sheng Huang, Tay-Jyi Lin, Shih-Hao Ou, Chih-Wei Liu, Chein-Wei Jen
    Pipelining technique for energy-aware datapaths. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1218-1221 [Conf]
  12. Tay-Jyi Lin, Tsung-Hsun Yang, Chein-Wei Jen
    Area-effective FIR filter design for multiplier-less implementation. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:173-176 [Conf]
  13. Yu-Sheng Lin, Jiun-In Guo, C. Bernard Shung, Chein-Wei Jen
    A Multi-phase Shared Bus Structure for the Fast Fourier Transform. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1575-1578 [Conf]
  14. Jiann-Jenn Wang, Chein-Wei Jen
    A High Throughput Systolic Design for QR Algorithm. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1742-1745 [Conf]
  15. Yuan-Chung Lee, Chein-Wei Jen
    Arbitrarily scalable edge-preserving interpolation for 3-D graphics and video resizing. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:317-320 [Conf]
  16. Ilion Yi-Liang Hsiao, Ding-Hao Wang, Chein-Wei Jen
    Power modeling and low-power design of content addressable memories. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:926-929 [Conf]
  17. Tay-Jyi Lin, Chein-Wei Jen
    An efficient 2-D DWT architecture via resource cycling. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:914-917 [Conf]
  18. Kun-Bin Lee, Hui-Cheng Hsu, Chein-Wei Jen
    A cost-effective MPEG-4 shape-adaptive DCT with auto-aligned transpose memory organization. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:777-780 [Conf]
  19. Hung-Yueh Lin, Tay-Jyi Lin, Chie-Min Chao, Yen-Chin Liao, Chih-Wei Liu, Chein-Wei Jen
    Static floating-point unit with implicit exponent tracking for embedded DSP. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:821-824 [Conf]
  20. Nelson Yen-Chung Chang, Kun-Bin Lee, Chein-Wei Jen
    Trace-path analysis and performance estimation for multimedia application in embedded system. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:129-132 [Conf]
  21. Kun-Bin Lee, Hao-Yun Chin, Hui-Cheng Hsu, Chein-Wei Jen
    QME: an efficient subsampling-based block matching algorithm for motion estimation. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:305-308 [Conf]
  22. Kun-Bin Lee, Jih-Yiing Lin, Chein-Wei Jen
    A fast dual symbol context-based arithmetic coding for MPEG-4 shape coding. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:317-320 [Conf]
  23. Hun-Chen Chen, Jiun-In Guo, Chein-Wei Jen
    A new group distributed arithmetic design for the one dimensional discrete Fourier transform. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2002, pp:421-424 [Conf]
  24. Tay-Jyi Lin, Chein-Wei Jen
    CASCADE - configurable and scalable DSP environment. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:870-873 [Conf]
  25. Yun-Tai Hsiao, Hung-Der Lin, Kun-Bin Lee, Chein-Wei Jen
    High-speed memory-saving architecture for the embedded block coding in JPEG2000. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:133-136 [Conf]
  26. Sun-Yuan Kung, Chih-Wei Jim Chang, Chein-Wei Jen
    Real-Time Configuration for Fault-Tolerant VLSI Array Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Real-Time Systems Symposium, 1986, pp:46-54 [Conf]
  27. Chein-Wei Jen, Ding-Ming Kwai
    Data Flow Representation of Iterative Algorithms for Systolic Arrays. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1992, v:41, n:3, pp:351-355 [Journal]
  28. Wen-Chang Yeh, Chein-Wei Jen
    High-Speed Booth Encoded Parallel Multiplier Design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2000, v:49, n:7, pp:692-701 [Journal]
  29. Wen-Chang Yeh, Chein-Wei Jen
    Generalized Earliest-First Fast Addition Algorithm. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2003, v:52, n:10, pp:1233-1242 [Journal]
  30. Tian-Sheuan Chang, Chin-Sheng Kung, Chein-Wei Jen
    A simple processor core design for DCT/IDCT. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Circuits Syst. Video Techn., 2000, v:10, n:3, pp:439-447 [Journal]
  31. Hun-Chen Chen, Jiun-In Guo, Tian-Sheuan Chang, Chein-Wei Jen
    A memory-efficient realization of cyclic convolution and its application to discrete cosine transform. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Circuits Syst. Video Techn., 2005, v:15, n:3, pp:445-453 [Journal]
  32. Kun-Bin Lee, Jih-Yiing Lin, Chein-Wei Jen
    A multisymbol context-based arithmetic coding architecture for MPEG-4 shape coding. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Circuits Syst. Video Techn., 2005, v:15, n:2, pp:283-295 [Journal]
  33. Kun-Bin Lee, Tzu-Chieh Lin, Chein-Wei Jen
    An Efficient Quality-Aware Memory Controller for Multimedia Platform SoC. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Circuits Syst. Video Techn., 2005, v:15, n:5, pp:620-633 [Journal]
  34. Jen-Chieh Tuan, Tian-Sheuan Chang, Chein-Wei Jen
    On the data reuse and memory bandwidth analysis for full-search block-matching VLSI architecture. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Circuits Syst. Video Techn., 2002, v:12, n:1, pp:61-72 [Journal]
  35. Bor-Sung Liang, Yuan-Chung Lee, Wen-Chang Yeh, Chein-Wei Jen
    Index rendering: hardware-efficient architecture for 3-D graphics in multimedia system. [Citation Graph (0, 0)][DBLP]
    IEEE Transactions on Multimedia, 2002, v:4, n:3, pp:343-360 [Journal]
  36. Yuan-Chung Lee, Chein-Wei Jen
    Improved quadratic normal vector interpolation for realistic shading. [Citation Graph (0, 0)][DBLP]
    The Visual Computer, 2001, v:17, n:6, pp:337-352 [Journal]
  37. Yuan-Chung Lee, Chein-Wei Jen
    Edge-preserving texture filtering for real-time rendering. [Citation Graph (0, 0)][DBLP]
    The Visual Computer, 2003, v:19, n:1, pp:10-22 [Journal]
  38. Pi-Chen Hsiao, Tay-Jyi Lin, Chih-Wei Liu, Chein-Wei Jen
    Latency-Tolerant Virtual Cluster Architecture for VLIW DSP. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3506-3509 [Conf]
  39. Yu-Ting Kuo, Tay-Jyi Lin, Yi Cho, Chih-Wei Liu, Chein-Wei Jen
    Programmable FIR filter with adder-based computing engine. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]

  40. PAC DSP Core and Application Processors. [Citation Graph (, )][DBLP]


  41. Architecture for area-efficient 2-D transform in H.264/AVC. [Citation Graph (, )][DBLP]


  42. Hierarchical instruction encoding for VLIW digital signal processors. [Citation Graph (, )][DBLP]


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