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Gi-Yong Song :
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Jae-Jin Lee , Gi-Yong Song Design of an application-specific PLD architecture. [Citation Graph (0, 0)][DBLP ] ASP-DAC, 2005, pp:1244-1247 [Conf ] Jae-Jin Lee , Gi-Yong Song Bit-level super-systolic array for FIR filter with a FPGA-based bit-serial semi-systolic multiplier. [Citation Graph (0, 0)][DBLP ] FPGA, 2004, pp:249- [Conf ] Jae-Jin Lee , Gi-Yong Song High-Level Synthesis Using SPARK and Systolic Array. [Citation Graph (0, 0)][DBLP ] ARC, 2006, pp:455-460 [Conf ] Jae-Jin Lee , Gi-Yong Song Super Semi-systolic Array-Based Application-Specific PLD Architecture. [Citation Graph (0, 0)][DBLP ] ARC, 2006, pp:461-466 [Conf ] Jae-Jin Lee , Dong-Guk Hwang , Gi-Yong Song Design of a Reversible PLD Architecture. [Citation Graph (0, 0)][DBLP ] ARC, 2007, pp:85-90 [Conf ] Search in 0.001secs, Finished in 0.001secs