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Haris Lekatsas: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Haris Lekatsas, Jörg Henkel
    ETAM++: Extended Transition Activity Measure for Low Power Address Bus Designs. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:113-120 [Conf]
  2. Haris Lekatsas, Jörg Henkel, Wayne Wolf
    Code compression as a variable in hardware/software co-design. [Citation Graph (0, 0)][DBLP]
    CODES, 2000, pp:120-124 [Conf]
  3. Lei Yang, Robert P. Dick, Haris Lekatsas, Srimat T. Chakradhar
    CRAMES: compressed RAM for embedded systems. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2005, pp:93-98 [Conf]
  4. Jörg Henkel, Haris Lekatsas
    A2BC: Adaptive Address Bus Coding for Low Power Deep Sub-Micron Designs. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:744-749 [Conf]
  5. Haris Lekatsas, Jörg Henkel, Srimat T. Chakradhar, Venkata Jakkula, Murugan Sankaradass
    CoCo: a hardware/software platform for rapid prototyping of code compression technologies. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:306-311 [Conf]
  6. Haris Lekatsas, Jörg Henkel, Venkata Jakkula
    Design of an one-cycle decompression hardware for performance increase in embedded systems. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:34-39 [Conf]
  7. Haris Lekatsas, Jörg Henkel, Wayne Wolf
    Code compression for low power embedded system design. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:294-299 [Conf]
  8. Haris Lekatsas, Wayne Wolf
    Code Compression for Embedded Systems. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:516-521 [Conf]
  9. Lei Yang, Haris Lekatsas, Robert P. Dick
    High-performance operating system controlled memory compression. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:701-704 [Conf]
  10. Tiehan Lv, Jörg Henkel, Haris Lekatsas, Wayne Wolf
    Enhancing Signal Integrity through a Low-Overhead Encoding Scheme on Address Buses. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10542-10549 [Conf]
  11. Tiehan Lv, Wayne Wolf, Jörg Henkel, Haris Lekatsas
    An Adaptive Dictionary Encoding Scheme for SOC Data Buses. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:1059- [Conf]
  12. Yuan Xie, Wayne Wolf, Haris Lekatsas
    Profile-Driven Selective Code Compression. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10462-10467 [Conf]
  13. Haris Lekatsas, Wayne Wolf
    Random Access Decompression Using Binary Arithmetic Coding. [Citation Graph (0, 0)][DBLP]
    Data Compression Conference, 1999, pp:306-315 [Conf]
  14. Haris Lekatsas, Wayne Wolf, Jörg Henkel
    Arithmetic Coding for Low Power Embedded System Design. [Citation Graph (0, 0)][DBLP]
    Data Compression Conference, 2000, pp:430-439 [Conf]
  15. Yuan Xie, Haris Lekatsas, Wayne Wolf
    Code Compression for VLIW Processors. [Citation Graph (0, 0)][DBLP]
    Data Compression Conference, 2001, pp:525- [Conf]
  16. Yuan Xie, Wayne Wolf, Haris Lekatsas
    Code Compression Using Variable-to-fixed Coding Based on Arithmetic Coding. [Citation Graph (0, 0)][DBLP]
    DCC, 2003, pp:382-391 [Conf]
  17. Haris Lekatsas, Jörg Henkel, Wayne Wolf
    A Decompression Architecture for Low Power Embedded Systems. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:571-574 [Conf]
  18. Haris Lekatsas, Jörg Henkel, Wayne Wolf
    Design and simulation of a pipelined decompression architecture for embedded systems. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:63-68 [Conf]
  19. Haris Lekatsas, Wayne Wolf, Yuan Xie
    Code Compression for VLIW Processors Using Variable-to-Fixed Coding. [Citation Graph (0, 0)][DBLP]
    ISSS, 2002, pp:138-143 [Conf]
  20. Yuan Xie, Wayne Wolf, Haris Lekatsas
    A code decompression architecture for VLIW processors. [Citation Graph (0, 0)][DBLP]
    MICRO, 2001, pp:66-75 [Conf]
  21. Haris Lekatsas, Jörg Henkel
    ETAM++: Extended Transition Activity Measure for Low Power Address Bus Designs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:113-120 [Conf]
  22. Haris Lekatsas, Jörg Henkel, Venkata Jakkula, Srimat T. Chakradhar
    A Unified Architecture for Adaptive Compression of Data and Code on Embedded Systems. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:117-123 [Conf]
  23. Haris Lekatsas, Jörg Henkel, Venkata Jakkula, Srimat T. Chakradhar
    Using Shiftable Content Addressable Memories to Double Memory Capacity on Embedded Systems. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:639-644 [Conf]
  24. Haris Lekatsas, Jörg Henkel, Srimat T. Chakradhar, Venkata Jakkula
    Cypress: Compression and Encryption of Data and Code for Embedded Multimedia Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2004, v:21, n:5, pp:406-415 [Journal]
  25. Haris Lekatsas, Wayne Wolf
    SAMC: a code compression algorithm for embedded processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:12, pp:1689-1701 [Journal]
  26. Dimitrios N. Serpanos, Haris Lekatsas
    Guest editorial: Special issue on embedded systems and security. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2004, v:3, n:3, pp:459-460 [Journal]
  27. Haris Lekatsas, Jörg Henkel, Wayne Wolf
    Approximate arithmetic coding for bus transition reduction in low power designs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:6, pp:696-707 [Journal]
  28. Yuan Xie, Wayne Wolf, Haris Lekatsas
    Code Compression for Embedded VLIW Processors Using Variable-to-Fixed Coding. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:5, pp:525-536 [Journal]
  29. Yuan Xie, Wayne Wolf, Haris Lekatsas
    Code Decompression Unit Design for VLIW Embedded Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:8, pp:975-980 [Journal]
  30. Tiehan Lv, Jörg Henkel, Haris Lekatsas, Wayne Wolf
    A dictionary-based en/decoding scheme for low-power data buses. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:5, pp:943-951 [Journal]

  31. Adaptive Filesystem Compression for Embedded Systems. [Citation Graph (, )][DBLP]


  32. Design and Implementation of a High-Performance Microprocessor Cache Compression Algorithm. [Citation Graph (, )][DBLP]


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