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Hai Li: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Hai Li, Yiran Chen, Kaushik Roy, Cheng-Kok Koh
    SAVS: a self-adaptive variable supply-voltage technique for process- tolerant and power-efficient multi-issue superscalar processor design. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:158-163 [Conf]
  2. Swarup Bhunia, Hai Li, Kaushik Roy
    A High Performance IDDQ Testable Cache for Scaled CMOS Technologies. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2002, pp:157-0 [Conf]
  3. Amit Agarwal, Hai Li, Kaushik Roy
    DRG-cache: a data retention gated-ground cache for low power. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:473-478 [Conf]
  4. Hai Li, Swarup Bhunia, Yiran Chen, T. N. Vijaykumar, Kaushik Roy
    Deterministic Clock Gating for Microprocessor Power Reduction. [Citation Graph (0, 0)][DBLP]
    HPCA, 2003, pp:113-0 [Conf]
  5. Hai Li, Tianming Liu, Geoffrey Young, Lei Guo, Stephen T. C. Wong
    Brain tissue segmentation based on DWI/DTI data. [Citation Graph (0, 0)][DBLP]
    ISBI, 2006, pp:57-60 [Conf]
  6. Yiran Chen, Hai Li, Kaushik Roy, Cheng-Kok Koh
    Cascaded carry-select adder (C2SA): a new structure for low-power CSA design. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:115-118 [Conf]
  7. Hai Li, Chen-Yong Cher, T. N. Vijaykumar, Kaushik Roy
    VSV: L2-Miss-Driven Variable Supply-Voltage Scaling for Low Power. [Citation Graph (0, 0)][DBLP]
    MICRO, 2003, pp:19-28 [Conf]
  8. Hai Li, Mark Fisher, Moe Razaz
    Compile-Time Task Scheduling using a Fuzzy Inference System. [Citation Graph (0, 0)][DBLP]
    Parallel and Distributed Computing and Networks, 2005, pp:546-550 [Conf]
  9. Hai Li, Swarup Bhunia, Yiran Chen, Kaushik Roy, T. N. Vijaykumar
    DCG: deterministic clock-gating for low-power microprocessor design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:3, pp:245-254 [Journal]
  10. Hai Li, Chen-Yong Cher, Kaushik Roy, T. N. Vijaykumar
    Combined circuit and architectural level variable supply-voltage scaling for low power. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:5, pp:564-576 [Journal]
  11. Ian W. Marshall, Mark C. Price, Hai Li, N. Boyd, Steve Boult
    Multi-sensor Cross Correlation for Alarm Generation in a Deployed Sensor Network. [Citation Graph (0, 0)][DBLP]
    EuroSSC, 2007, pp:286-299 [Conf]
  12. Hai Li, Mark C. Price, Jonathan Stott, Ian W. Marshall
    The Development of a Wireless Sensor Network Sensing Node Utilising Adaptive Self-diagnostics. [Citation Graph (0, 0)][DBLP]
    IWSOS, 2007, pp:30-43 [Conf]

  13. An overview of non-volatile memory technology and the implication for tools and architectures. [Citation Graph (, )][DBLP]

  14. Compact model of memristors and its application in computing systems. [Citation Graph (, )][DBLP]

  15. A nondestructive self-reference scheme for Spin-Transfer Torque Random Access Memory (STT-RAM). [Citation Graph (, )][DBLP]

  16. VOSCH: Voltage scaled cache hierarchies. [Citation Graph (, )][DBLP]

  17. Simultaneous Consideration of Spatial Deformation and Tensor Orientation in Diffusion Tensor Image Registration Using Local Fast Marching Patterns. [Citation Graph (, )][DBLP]

  18. Deformable Registration of Dti and Spgr Images. [Citation Graph (, )][DBLP]

  19. Variable-latency adder (VL-adder): new arithmetic circuit design practice to overcome NBTI. [Citation Graph (, )][DBLP]

  20. Combined magnetic- and circuit-level enhancements for the nondestructive self-reference scheme of STT-RAM. [Citation Graph (, )][DBLP]

  21. Design Margin Exploration of Spin-Torque Transfer RAM (SPRAM). [Citation Graph (, )][DBLP]

  22. Scalability of PCMO-based resistive switch device in DSM technologies. [Citation Graph (, )][DBLP]

  23. Distinguishing Left or Right Temporal Lobe Epilepsy from Controls Using Fractional Anisotropy Asymmetry Analysis. [Citation Graph (, )][DBLP]

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