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Jwu E. Chen: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Katherine Shu-Min Li, Yao-Wen Chang, Chauchin Su, Chung-Len Lee, Jwu E. Chen
    IEEE standard 1500 compatible interconnect diagnosis for delay and crosstalk faults. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:366-371 [Conf]
  2. Katherine Shu-Min Li, Chung-Len Lee, Chauchin Su, Jwu E. Chen
    Oscillation ring based interconnect test scheme for SOC. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:184-187 [Conf]
  3. Jwu E. Chen
    Yield Improvement by Test Error Cancellation. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1996, pp:258-262 [Conf]
  4. Guan-Xun Chen, Chung-Len Lee, Jwu E. Chen
    A New BIST Scheme Based on a Summing-into-Timing-Signal Principle with Self Calibration for the DAC. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2004, pp:58-61 [Conf]
  5. Jwu E. Chen, Chung-Len Lee, Wen-Zen Shen, Beyin Chen
    Fanout fault analysis for digital logic circuits. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1995, pp:33-39 [Conf]
  6. Chih Wei Hu, Chung-Len Lee, Wen Ching Wu, Jwu E. Chen
    Fault diagnosis of odd-even sorting networks. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1997, pp:288-0 [Conf]
  7. Yin-Chao Huang, Chung-Len Lee, Jun-Weir Lin, Jwu E. Chen, Chauchin Su
    A methodology for fault model development for hierarchical linear systems. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2000, pp:90-95 [Conf]
  8. Chin-Te Kao, Sam Wu, Jwu E. Chen
    A case study of failure analysis and guardband determination for a 64M-bit DRAM. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2000, pp:447-0 [Conf]
  9. Katherine Shu-Min Li, Chung-Len Lee, Tagin Jiang, Chauchin Su, Jwu E. Chen
    Finite State Machine Synthesis for At-Speed Oscillation Testability. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2005, pp:360-365 [Conf]
  10. Katherine Shu-Min Li, Chung-Len Lee, Chauchin Su, Jwu E. Chen
    A Unified Approach to Detecting Crosstalk Faults of Interconnects in Deep Sub-Micron VLSI. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2004, pp:145-150 [Conf]
  11. Hsing-Chung Liang, Chung-Len Lee, Jwu E. Chen
    Invalid State Identification for Sequential Circuit Test Generation. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1996, pp:10-15 [Conf]
  12. Chih-Wen Lu, Chauchin Su, Chung-Len Lee, Jwu E. Chen
    Is IDDQ testing not applicable for deep submicron VLSI in year 2011? [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2000, pp:338-343 [Conf]
  13. Shih Ping Lin, Chung-Len Lee, Jwu E. Chen
    A Scan Matrix Design for Low Power Scan-Based Test. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2005, pp:224-229 [Conf]
  14. Shih Ping Lin, Chung-Len Lee, Jwu E. Chen
    Adaptive Encoding Scheme for Test Volume/Time Reduction in SoC Scan Testing. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2005, pp:324-329 [Conf]
  15. Jun-Weir Lin, Chung-Len Lee, Chauchin Su, Jwu E. Chen
    Fault diagnosis for linear analog circuits. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2000, pp:25-30 [Conf]
  16. Mill-Jer Wang, R.-L. Jiang, J.-W. Hsia, Chih-Hu Wang, Jwu E. Chen
    Guardband Determination for the Detection of Off-State and Junction Leakages in DRAM Testing. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2001, pp:151-156 [Conf]
  17. Wen Ching Wu, Chung-Len Lee, Jwu E. Chen
    Identification of robust untestable path delay faults. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1995, pp:229-0 [Conf]
  18. Ming Shae Wu, Chung-Len Lee, Chi Peng Chang, Jwu E. Chen
    A Testing Scheme for Crosstalk Faults Based on the Oscillation Test Signal. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2002, pp:170-175 [Conf]
  19. Jun-Weir Lin, Chung-Len Lee, Jwu E. Chen
    An Efficient Test and Diagnosis Scheme for the Feedback Type of Analog Circuits with Minimal Added Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:1119- [Conf]
  20. Meng Chiy Lin, Jwu E. Chen, Chung-Len Lee
    TRANS: A Fast and Memory-Efficient Path Delay Fault Simulator. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:508-512 [Conf]
  21. Wen Ching Wu, Chung-Len Lee, Jwu E. Chen, Won Yih Lin
    Distributed Fault Simulation for Sequential Circuits by Pattern Partitioning. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:661- [Conf]
  22. Hui Min Wang, Chung-Len Lee, Jwu E. Chen
    Fault Analysis on Two-Level (K+1)-Valued Logic Circuits. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1992, pp:181-188 [Conf]
  23. Hui Min Wang, Chung-Len Lee, Jwu E. Chen
    Algebraic Division for Multilevel Logic Synthesis of Multi-Valued Logic Circuits. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1994, pp:44-51 [Conf]
  24. Hui Min Wang, Chung-Len Lee, Jwu E. Chen
    Complete Test Set for Multiple-Valued Logic Networks. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1994, pp:289-296 [Conf]
  25. Hui Min Wang, Chung-Len Lee, Jwu E. Chen
    Factorization of Multi-Valued Logic Functions. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1995, pp:164-169 [Conf]
  26. Kuo-Chan Huang, Chung-Len Lee, Jwu E. Chen
    Maximization of power dissipation under random excitation for burn-in testing. [Citation Graph (0, 0)][DBLP]
    ITC, 1998, pp:567-576 [Conf]
  27. Katherine Shu-Min Li, Chung-Len Lee, Yao-Wen Chang, Chauchin Su, Jwu E. Chen
    Multilevel full-chip routing with testability and yield enhancement. [Citation Graph (0, 0)][DBLP]
    SLIP, 2005, pp:29-36 [Conf]
  28. Soon Jyh Chang, Chung-Len Lee, Jwu E. Chen
    Functional test pattern generation for CMOS operational amplifier. [Citation Graph (0, 0)][DBLP]
    VTS, 1997, pp:267-273 [Conf]
  29. Hsing-Chung Liang, Chung-Len Lee, Jwu E. Chen
    Partial Reset and Scan for Flip-Flops Based on States Requirement for Test Generation. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:341-347 [Conf]
  30. Hsing-Chung Liang, Chung-Len Lee, Jwu E. Chen
    Identifying Untestable Faults in Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1995, v:12, n:3, pp:14-23 [Journal]
  31. Soon Jyh Chang, Chung-Len Lee, Jwu E. Chen
    Structure-Based Specification-Constrained Test Frequency Generation for Linear Analog Circuits. [Citation Graph (0, 0)][DBLP]
    J. Inf. Sci. Eng., 2003, v:19, n:4, pp:637-651 [Journal]
  32. Yeong-Jar Chang, Chung-Len Lee, Jwu E. Chen, Chauchin Su
    A Behavior-Level Fault Model for the Closed-Loop Operational Amplifier. [Citation Graph (0, 0)][DBLP]
    J. Inf. Sci. Eng., 2000, v:16, n:5, pp:751-766 [Journal]
  33. Kuo-Chan Huang, Chung-Len Lee, Jwu E. Chen
    A Compiled-Code Parallel Pattern Logic Simulator With Inertial Delay Model. [Citation Graph (0, 0)][DBLP]
    J. Inf. Sci. Eng., 1999, v:15, n:6, pp:885-897 [Journal]
  34. Wen Ching Wu, Chung-Len Lee, Jwu E. Chen
    A Two-Phase Fault Simulation Scheme for Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    J. Inf. Sci. Eng., 1998, v:14, n:3, pp:669-686 [Journal]
  35. Jwu E. Chen, Chung-Len Lee, Wen-Zen Shen
    Single-fault fault-collapsing analysis in sequential logic circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:12, pp:1559-1568 [Journal]
  36. Katherine Shu-Min Li, Chauchin Su, Yao-Wen Chang, Chung-Len Lee, Jwu E. Chen
    IEEE Standard 1500 Compatible Interconnect Diagnosis for Delay and Crosstalk Faults. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:11, pp:2513-2525 [Journal]
  37. Hsing-Chung Liang, Chung-Len Lee, Jwu E. Chen
    Identifying invalid states for sequential circuit test generation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:9, pp:1025-1033 [Journal]
  38. Katherine Shu-Min Li, Chung-Len Lee, Chauchin Su, Jwu E. Chen
    IEEE Standard 1500 Compatible Oscillation Ring Test Methodology for Interconnect Delay and Crosstalk Detection. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2007, v:23, n:4, pp:341-355 [Journal]

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