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Patrick H. Madden: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Chen Li 0004, Cheng-Kok Koh, Patrick H. Madden
    Floorplan management: incremental placement for gate sizing and buffer insertion. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:349-354 [Conf]
  2. Pradeep Ramachandaran, Ameya R. Agnihotri, Satoshi Ono, Purushothaman Damodaran, Krishnaswami Srihari, Patrick H. Madden
    Optimal placement by branch-and-price. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:337-342 [Conf]
  3. Satoshi Ono, Patrick H. Madden
    On structure and suboptimality in placement. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:331-336 [Conf]
  4. Faris H. Khundakjie, Patrick H. Madden, Nael B. Abu-Ghazaleh, Mehmet Can Yildiz
    Parallel Standard Cell Placement on a Cluster of Workstations. [Citation Graph (0, 0)][DBLP]
    CLUSTER, 2001, pp:85-94 [Conf]
  5. Jason Cong, Patrick H. Madden
    Performance Driven Multi-Layer General Area Routing for PCB/MCM Designs. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:356-361 [Conf]
  6. Raia T. Hadsell, Patrick H. Madden
    Improved global routing through congestion estimation. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:28-31 [Conf]
  7. Mehmet Can Yildiz, Patrick H. Madden
    Improved Cut Sequences for Partitioning Based Placement. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:776-779 [Conf]
  8. Ryon M. Smey, Bill Swartz, Patrick H. Madden
    Crosstalk Reduction in Area Routing. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10862-10867 [Conf]
  9. Ameya R. Agnihotri, Patrick H. Madden
    Congestion reduction in traditional and new routing architectures. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2003, pp:211-214 [Conf]
  10. Cheng-Kok Koh, Patrick H. Madden
    Manhattan or non-Manhattan?: a study of alternative VLSI routing architectures. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2000, pp:47-52 [Conf]
  11. Mehmet Can Yildiz, Patrick H. Madden
    Preferred direction Steiner trees. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2001, pp:56-61 [Conf]
  12. Mehmet Can Yildiz, Patrick H. Madden
    Global objectives for standard cell placement. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2001, pp:68-72 [Conf]
  13. Ameya R. Agnihotri, Mehmet Can Yildiz, Ateen Khatkhate, Ajita Mathur, Satoshi Ono, Patrick H. Madden
    Fractional Cut: Improved Recursive Bisection Placement. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:307-310 [Conf]
  14. Chen Li 0004, Min Xie, Cheng-Kok Koh, Jason Cong, Patrick H. Madden
    Routability-driven placement and white space allocation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:394-401 [Conf]
  15. Jason Cong, Patrick H. Madden
    Performance Driven Routing with Mulitiple Sources. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:203-206 [Conf]
  16. Jason Cong, Patrick H. Madden
    Performance driven global routing for standard cell design. [Citation Graph (0, 0)][DBLP]
    ISPD, 1997, pp:73-80 [Conf]
  17. Saurabh N. Adya, Mehmet Can Yildiz, Igor L. Markov, Paul Villarrubia, Phiroze N. Parakh, Patrick H. Madden
    Benchmarking for large-scale placement and beyond. [Citation Graph (0, 0)][DBLP]
    ISPD, 2003, pp:95-103 [Conf]
  18. Ameya R. Agnihotri, Satoshi Ono, Patrick H. Madden
    Recursive bisection placement: feng shui 5.0 implementation details. [Citation Graph (0, 0)][DBLP]
    ISPD, 2005, pp:230-232 [Conf]
  19. Ateen Khatkhate, Chen Li 0004, Ameya R. Agnihotri, Mehmet Can Yildiz, Satoshi Ono, Cheng-Kok Koh, Patrick H. Madden
    Recursive bisection based mixed block placement. [Citation Graph (0, 0)][DBLP]
    ISPD, 2004, pp:84-89 [Conf]
  20. Patrick H. Madden
    Reporting of standard cell placement results. [Citation Graph (0, 0)][DBLP]
    ISPD, 2001, pp:30-35 [Conf]
  21. Patrick H. Madden
    Partitioning by iterative deletion. [Citation Graph (0, 0)][DBLP]
    ISPD, 1999, pp:83-89 [Conf]
  22. Jason Cong, Lei He, Cheng-Kok Koh, Patrick H. Madden
    Performance optimization of VLSI interconnect layout. [Citation Graph (0, 0)][DBLP]
    Integration, 1996, v:21, n:1-2, pp:1-94 [Journal]
  23. Saurabh N. Adya, Mehmet Can Yildiz, Igor L. Markov, Paul Villarrubia, Phiroze N. Parakh, Patrick H. Madden
    Benchmarking for large-scale placement and beyond. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:4, pp:472-487 [Journal]
  24. Ameya R. Agnihotri, Satoshi Ono, Chen Li 0004, Mehmet Can Yildiz, Ateen Khatkhate, Cheng-Kok Koh, Patrick H. Madden
    Mixed block placement via fractional cut recursive bisection. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:5, pp:748-761 [Journal]
  25. Jason Cong, Cheng-Kok Koh, Patrick H. Madden
    Interconnect layout optimization under higher order RLC model forMCM designs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:12, pp:1455-1463 [Journal]
  26. Jason Cong, Patrick H. Madden
    Performance-driven routing with multiple sources. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:4, pp:410-419 [Journal]
  27. Wen-Ben Jone, Patrick H. Madden
    Multiple fault testing using minimal single fault test set for fanout-free circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:1, pp:149-157 [Journal]
  28. Patrick H. Madden
    Reporting of standard cell placement results. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:2, pp:240-247 [Journal]
  29. Mehmet Can Yildiz, Patrick H. Madden
    Preferred direction Steiner trees. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:11, pp:1368-1372 [Journal]
  30. Gi-Joon Nam, Mehmet Can Yildiz, David Z. Pan, Patrick H. Madden
    ISPD placement contest updates and ISPD 2007 global routing contest. [Citation Graph (0, 0)][DBLP]
    ISPD, 2007, pp:167- [Conf]

  31. Fast Analytic Placement using Minimum Cost Flow. [Citation Graph (, )][DBLP]


  32. Bisection Based Placement for the X Architecture. [Citation Graph (, )][DBLP]


  33. An effective approach for large scale floorplanning. [Citation Graph (, )][DBLP]


  34. Performance analysis by topology indexed lookup tables. [Citation Graph (, )][DBLP]


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