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Shoujun Wang: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Miao Li, Tad A. Kwasniewski, Shoujun Wang, Yuming Tao
    A 10Gb/s transmitter with multi-tap FIR pre-emphasis in 0.18µm CMOS technology. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:679-682 [Conf]
  2. Wm. Bereza, Yuming Tao, Shoujun Wang, Tad A. Kwasniewski, Rakesh H. Patel
    PELE: pre-emphasis & equalization link estimator to address the effects of signal integrity limitations. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:1013-1016 [Conf]
  3. Miao Li, Wenjie Huang, Tad A. Kwasniewski, Shoujun Wang
    A 0.18µm CMOS transceiver design for high-speed backplane data communications. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1158-1161 [Conf]
  4. Miao Li, Peter Noel, Tad A. Kwasniewski, Shoujun Wang
    Decision Feedback Equalization with Quarter-Rate Clock Timing for High-Speed Backplane Data Communications. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2005, pp:500-502 [Conf]
  5. Miao Li, Wenjie Huang, Tad A. Kwasniewski, Shoujun Wang
    A 0.18µm CMOS clock and data recovery circuit with extended operation range. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]

  6. A 0.18-µm CMOS clock and data recovery circuit with reference-less dual loops. [Citation Graph (, )][DBLP]


  7. A 0.18µm CMOS Receiver with Decision-feedback Equalization for Backplane Applications. [Citation Graph (, )][DBLP]


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