The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Charles J. Alpert: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Chuck J. Alpert, Gi-Joon Nam, Paul Villarribua, Mehmet Can Yildiz
    Placement stability metrics. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:1144-1147 [Conf]
  2. Zhuo Li, Cliff C. N. Sze, Charles J. Alpert, Jiang Hu, Weiping Shi
    Making fast buffer insertion even faster via approximation techniques. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:13-18 [Conf]
  3. Cliff C. N. Sze, Jiang Hu, Charles J. Alpert
    A place and route aware buffered Steiner tree construction. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:355-360 [Conf]
  4. Weiping Shi, Zhuo Li, Charles J. Alpert
    Complexity analysis and speedup techniques for optimal buffer insertion with minimum cost. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:609-614 [Conf]
  5. Charles J. Alpert, Andrew B. Kahng
    Geometric Embeddings for Faster and Better Multi-Way Netlist Partitioning. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:743-748 [Conf]
  6. Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Paul Villarrubia
    A Practical Methodology for Early Buffer and Wire Resource Allocation. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:189-194 [Conf]
  7. Charles J. Alpert, Andrew B. Kahng
    Multi-Way Partitioning Via Spacefilling curves and Dynamic Programming. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:652-657 [Conf]
  8. Charles J. Alpert, Andrew B. Kahng, Cliff C. N. Sze, Qinke Wang
    Timing-driven Steiner trees are (practically) free. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:389-392 [Conf]
  9. Charles J. Alpert, Frank Liu, Chandramouli V. Kashyap, Anirudh Devgan
    Delay and slew metrics using the lognormal distribution. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:382-385 [Conf]
  10. Charles J. Alpert, So-Zen Yao
    Spectral Partitioning: The More Eigenvectors, The Better. [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:195-200 [Conf]
  11. Charles J. Alpert, Tony F. Chan, Dennis J.-H. Huang, Igor L. Markov, Kenneth Yan
    Quadratic Placement Revisited. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:752-757 [Conf]
  12. Charles J. Alpert, Anirudh Devgan
    Wire Segmenting for Improved Buffer Insertion. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:588-593 [Conf]
  13. Charles J. Alpert, Anirudh Devgan, Stephen T. Quay
    Buffer Insertion for Noise and Delay Optimization. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:362-367 [Conf]
  14. Charles J. Alpert, Anirudh Devgan, Stephen T. Quay
    Buffer Insertion with Accurate Gate and Interconnect Delay Computation. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:479-484 [Conf]
  15. Charles J. Alpert, Milos Hrkic, Jiang Hu, Stephen T. Quay
    Fast and flexible buffer trees that navigate the physical layout environment. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:24-29 [Conf]
  16. Charles J. Alpert, Jen-Hsin Huang, Andrew B. Kahng
    Multilevel Circuit Partitioning. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:530-533 [Conf]
  17. Shiyan Hu, Charles J. Alpert, Jiang Hu, Shrirang K. Karandikar, Zhuo Li, Weiping Shi, Cliff C. N. Sze
    Fast algorithms for slew constrained minimum cost buffering. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:308-313 [Conf]
  18. Haoxing Ren, David Zhigang Pan, Charles J. Alpert, Paul Villarrubia
    Diffusion-based placement migration. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:515-520 [Conf]
  19. Cliff C. N. Sze, Charles J. Alpert, Jiang Hu, Weiping Shi
    Path based buffer insertion. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:509-514 [Conf]
  20. Charles J. Alpert, Anirudh Devgan, Stephen T. Quay
    Is wire tapering worthwhile? [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:430-436 [Conf]
  21. Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Cliff C. N. Sze
    Accurate estimation of global buffer delay within a floorplan. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:706-711 [Conf]
  22. Charles J. Alpert, Andrew B. Kahng
    A general framework for vertex orderings, with applications to netlist clustering. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:63-67 [Conf]
  23. Charles J. Alpert, Andrew B. Kahng, Bao Liu, Ion I. Mandoiu, Alexander Zelikovsky
    Minimum-Buffered Routing of Non-Critical Nets for Slew Rate and Reliability Control. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:408-0 [Conf]
  24. Charles J. Alpert, Gi-Joon Nam, Paul Villarrubia
    Free space management for cut-based placement. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:746-751 [Conf]
  25. Soha Hassoun, Charles J. Alpert, Meera Thiagarajan
    Optimal buffered routing path constructions for single and multiple clock domain systems. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:247-253 [Conf]
  26. Chandramouli V. Kashyap, Charles J. Alpert, Anirudh Devgan
    An "Effective" Capacitance Based Delay Metric for RC Interconnect. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:229-234 [Conf]
  27. Frank Liu, Chandramouli V. Kashyap, Charles J. Alpert
    A delay metric for RC circuits based on the Weibull distribution. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:620-624 [Conf]
  28. Tao Luo, Haoxing Ren, Charles J. Alpert, David Zhigang Pan
    Computational geometry based placement migration. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:41-47 [Conf]
  29. Ganesh Venkataraman, Nikhil Jayakumar, Jiang Hu, Peng Li, Sunil P. Khatri, Anand Rajaram, Patrick McGuinness, Charles J. Alpert
    Practical techniques to reduce skew and its variations in buffered clock networks. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:592-596 [Conf]
  30. Charles J. Alpert, Jason Cong, Andrew B. Kahng, Gabriel Robins, Majid Sarrafzadeh
    Minimum Density Interconneciton Trees. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1865-1868 [Conf]
  31. Charles J. Alpert, T. C. Hu, Jen-Hsin Huang, Andrew B. Kahng
    A Direct Combination of the Prim and Dijkstra Constructions for Improved Performance-driven Global Routing. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1869-1872 [Conf]
  32. Charles J. Alpert, Gopal Gandham, Jiang Hu, José Luis Neves, Stephen T. Quay, Sachin S. Sapatnekar
    Steiner tree optimization for buffers. Blockages and bays. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:399-402 [Conf]
  33. Charles J. Alpert
    The ISPD98 circuit benchmark suite. [Citation Graph (0, 0)][DBLP]
    ISPD, 1998, pp:80-85 [Conf]
  34. Charles J. Alpert, Chris C. N. Chu, Gopal Gandham, Milos Hrkic, Jiang Hu, Chandramouli V. Kashyap, Stephen T. Quay
    Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique. [Citation Graph (0, 0)][DBLP]
    ISPD, 2002, pp:104-109 [Conf]
  35. Charles J. Alpert, Tony F. Chan, Dennis J.-H. Huang, Andrew B. Kahng, Igor L. Markov, Pep Mulet, Kenneth Yan
    Faster minimization of linear wirelength for global placement. [Citation Graph (0, 0)][DBLP]
    ISPD, 1997, pp:4-11 [Conf]
  36. Charles J. Alpert, Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov
    Partitioning with terminals: a "new" problem and new benchmarks. [Citation Graph (0, 0)][DBLP]
    ISPD, 1999, pp:151-157 [Conf]
  37. Charles J. Alpert, Anirudh Devgan, Chandramouli V. Kashyap
    A two moment RC delay metric for performance optimization. [Citation Graph (0, 0)][DBLP]
    ISPD, 2000, pp:69-74 [Conf]
  38. Charles J. Alpert, Gopal Gandham, Milos Hrkic, Jiang Hu, Stephen T. Quay
    Porosity aware buffered steiner tree construction. [Citation Graph (0, 0)][DBLP]
    ISPD, 2003, pp:158-165 [Conf]
  39. Charles J. Alpert, Milos Hrkic, Jiang Hu, Andrew B. Kahng, John Lillis, Bao Liu, Stephen T. Quay, Sachin S. Sapatnekar, A. J. Sullivan, Paul Villarrubia
    Buffered Steiner trees for difficult instances. [Citation Graph (0, 0)][DBLP]
    ISPD, 2001, pp:4-9 [Conf]
  40. Charles J. Alpert, Milos Hrkic, Stephen T. Quay
    A fast algorithm for identifying good buffer insertion candidate locations. [Citation Graph (0, 0)][DBLP]
    ISPD, 2004, pp:47-52 [Conf]
  41. Charles J. Alpert, Andrew B. Kahng, Gi-Joon Nam, Sherief Reda, Paul Villarrubia
    A semi-persistent clustering technique for VLSI circuit placement. [Citation Graph (0, 0)][DBLP]
    ISPD, 2005, pp:200-207 [Conf]
  42. Jiang Hu, Charles J. Alpert, Stephen T. Quay, Gopal Gandham
    Buffer insertion with adaptive blockage avoidance. [Citation Graph (0, 0)][DBLP]
    ISPD, 2002, pp:92-97 [Conf]
  43. Chandramouli V. Kashyap, Charles J. Alpert, Frank Liu, Anirudh Devgan
    Closed form expressions for extending step delay and slew metrics to ramp inputs. [Citation Graph (0, 0)][DBLP]
    ISPD, 2003, pp:24-31 [Conf]
  44. Suresh Raman, Sachin S. Sapatnekar, Charles J. Alpert
    Datapath routing based on a decongestion metric. [Citation Graph (0, 0)][DBLP]
    ISPD, 2000, pp:122-127 [Conf]
  45. Rajeev R. Rao, David Blaauw, Dennis Sylvester, Charles J. Alpert, Sani R. Nassif
    An efficient surface-based low-power buffer insertion algorithm. [Citation Graph (0, 0)][DBLP]
    ISPD, 2005, pp:86-93 [Conf]
  46. Gi-Joon Nam, Charles J. Alpert, Paul Villarrubia, Bruce Winter, Mehmet Can Yildiz
    The ISPD2005 placement contest and benchmark suite. [Citation Graph (0, 0)][DBLP]
    ISPD, 2005, pp:216-220 [Conf]
  47. Zhuo Li, Charles J. Alpert, Stephen T. Quay, Sachin S. Sapatnekar, Weiping Shi
    Probabilistic Congestion Prediction with Partial Blockages. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:841-846 [Conf]
  48. Chandramouli V. Kashyap, Charles J. Alpert, Frank Liu, Anirudh Devgan
    PERI: a technique for extending delay and slew metrics to ramp inputs. [Citation Graph (0, 0)][DBLP]
    Timing Issues in the Specification and Synthesis of Digital Systems, 2002, pp:57-62 [Conf]
  49. Charles J. Alpert, Andrew B. Kahng, So-Zen Yao
    Spectral Partitioning with Multiple Eigenvectors. [Citation Graph (0, 0)][DBLP]
    Discrete Applied Mathematics, 1999, v:90, n:1-3, pp:3-26 [Journal]
  50. Suresh Raman, Sachin S. Sapatnekar, Charles J. Alpert
    Probability-driven routing in a datapath environment. [Citation Graph (0, 0)][DBLP]
    Integration, 2002, v:31, n:2, pp:159-182 [Journal]
  51. Charles J. Alpert, Chris C. N. Chu, Gopal Gandham, Milos Hrkic, Jiang Hu, Chandramouli V. Kashyap, Stephen T. Quay
    Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:1, pp:136-141 [Journal]
  52. Charles J. Alpert, Jen-Hsin Huang, Andrew B. Kahng
    Multilevel circuit partitioning. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:8, pp:655-667 [Journal]
  53. Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Cliff C. N. Sze
    Accurate estimation of global buffer delay within a floorplan. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:6, pp:1140-1145 [Journal]
  54. Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, Paul Villarrubia
    A practical methodology for early buffer and wire resource allocation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:5, pp:573-583 [Journal]
  55. Charles J. Alpert, Andrew B. Kahng
    Multiway partitioning via geometric embeddings, orderings, and dynamic programming. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:11, pp:1342-1358 [Journal]
  56. Charles J. Alpert, Andrew B. Kahng, Bao Liu, Ion I. Mandoiu, Alexander Zelikovsky
    Minimum buffered routing with bounded capacitive load for slew rate and reliability control. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:3, pp:241-253 [Journal]
  57. Charles J. Alpert, Frank Liu, Chandramouli V. Kashyap, Anirudh Devgan
    Closed-form delay and slew metrics made easy. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:12, pp:1661-1669 [Journal]
  58. Charles J. Alpert, Gi-Joon Nam, Paul G. Villarrubia
    Effective free space management for cut-based placement via analytical constraint generation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:10, pp:1343-1353 [Journal]
  59. Charles J. Alpert, Sachin S. Sapatnekar
    Guest editorial. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:4, pp:385-386 [Journal]
  60. Charles J. Alpert, Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov
    Hypergraph partitioning with fixed vertices [VLSI CAD]. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:2, pp:267-272 [Journal]
  61. Charles J. Alpert, Tony F. Chan, Andrew B. Kahng, Igor L. Markov, Pep Mulet
    Faster minimization of linear wirelength for global placement. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:1, pp:3-13 [Journal]
  62. Charles J. Alpert, Anirudh Devgan, John P. Fishburn, Stephen T. Quay
    Interconnect synthesis without wire tapering. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:1, pp:90-104 [Journal]
  63. Charles J. Alpert, Anirudh Devgan, John P. Fishburn, Stephen T. Quay
    Correction to "interconnect synthesis without wire tapering". [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:4, pp:497-497 [Journal]
  64. Charles J. Alpert, Anirudh Devgan, Chandramouli V. Kashyap
    RC delay metrics for performance optimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:5, pp:571-582 [Journal]
  65. Charles J. Alpert, Anirudh Devgan, Stephen T. Quay
    Buffer insertion for noise and delay optimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:11, pp:1633-1645 [Journal]
  66. Charles J. Alpert, Gopal Gandham, Milos Hrkic, Jiang Hu, Stephen T. Quay, Cliff C. N. Sze
    Porosity-aware buffered Steiner tree construction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:4, pp:517-526 [Journal]
  67. Charles J. Alpert, Gopal Gandham, Jiang Hu, José Luis Neves, Stephen T. Quay, Sachin S. Sapatnekar
    Steiner tree optimization for buffers, blockages, and bays. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:4, pp:556-562 [Journal]
  68. Charles J. Alpert, T. C. Hu, Dennis J.-H. Huang, Andrew B. Kahng, David Karger
    Prim-Dijkstra tradeoffs for improved performance-driven routing tree design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:7, pp:890-896 [Journal]
  69. Soha Hassoun, Charles J. Alpert
    Optimal path routing in single- and multiple-clock domain systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:11, pp:1580-1588 [Journal]
  70. Jiang Hu, Charles J. Alpert, Stephen T. Quay, Gopal Gandham
    Buffer insertion with adaptive blockage avoidance. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:4, pp:492-498 [Journal]
  71. Chandramouli V. Kashyap, Charles J. Alpert, Frank Liu, Anirudh Devgan
    Closed-form expressions for extending step delay and slew metrics to ramp inputs for RC trees. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:4, pp:509-516 [Journal]
  72. Frank Liu, Chandramouli V. Kashyap, Charles J. Alpert
    A delay metric for RC circuits based on the Weibull distribution. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:3, pp:443-447 [Journal]
  73. Gi-Joon Nam, Sherief Reda, Charles J. Alpert, Paul Villarrubia, Andrew B. Kahng
    A Fast Hierarchical Quadratic Placement Algorithm. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:4, pp:678-691 [Journal]
  74. Natarajan Viswanathan, Gi-Joon Nam, Charles J. Alpert, Paul Villarrubia, Haoxing Ren, Chris Chu
    RQL: Global Placement via Relaxed Quadratic Spreading and Linearization. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:453-458 [Conf]
  75. Charles J. Alpert, Shrirang K. Karandikar, Zhuo Li, Gi-Joon Nam, Stephen T. Quay, Haoxing Ren, Cliff C. N. Sze, Paul G. Villarrubia, Mehmet Can Yildiz
    The nuts and bolts of physical synthesis. [Citation Graph (0, 0)][DBLP]
    SLIP, 2007, pp:89-94 [Conf]
  76. Charles J. Alpert, Andrew B. Kahng
    A general framework for vertex orderings with applications to circuit clustering. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1996, v:4, n:2, pp:240-246 [Journal]

  77. Fast Electrical Correction Using Resizing and Buffering. [Citation Graph (, )][DBLP]


  78. Hippocrates: First-Do-No-Harm Detailed Placement. [Citation Graph (, )][DBLP]


  79. Path smoothing via discrete optimization. [Citation Graph (, )][DBLP]


  80. A fully polynomial time approximation scheme for timing driven minimum cost buffer insertion. [Citation Graph (, )][DBLP]


  81. Detecting tangled logic structures in VLSI netlists. [Citation Graph (, )][DBLP]


  82. The coming of age of physical synthesis. [Citation Graph (, )][DBLP]


  83. Pyramids: an efficient computational geometry-based approach for timing-driven placement. [Citation Graph (, )][DBLP]


  84. A polynomial time approximation scheme for timing constrained minimum cost layer assignment. [Citation Graph (, )][DBLP]


  85. CRISP: Congestion reduction by iterated spreading during placement. [Citation Graph (, )][DBLP]


  86. Ispd2009 clock network synthesis contest. [Citation Graph (, )][DBLP]


  87. RUMBLE: an incremental, timing-driven, physical-synthesis optimization algorithm. [Citation Graph (, )][DBLP]


  88. Fast interconnect synthesis with layer assignment. [Citation Graph (, )][DBLP]


  89. What makes a design difficult to route. [Citation Graph (, )][DBLP]


  90. A faster approximation scheme for timing driven minimum cost layer assignment. [Citation Graph (, )][DBLP]


  91. ITOP: integrating timing optimization within placement. [Citation Graph (, )][DBLP]


  92. Ultra-fast interconnect driven cell cloning for minimizing critical path delay. [Citation Graph (, )][DBLP]


Search in 0.031secs, Finished in 0.036secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002