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Zhonghai Lu: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Zhonghai Lu, Axel Jantsch, Ingo Sander
    Feasibility analysis of messages for on-chip networks using wormhole routing. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:960-964 [Conf]
  2. Ingo Sander, Axel Jantsch, Zhonghai Lu
    Development and Application of Design Transformations in ForSyDe. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10364-10369 [Conf]
  3. Zhonghai Lu, Ingo Sander, Axel Jantsch
    Towards Performance-Oriented Pattern-Based Refinement of Synchronous Models onto NoC Communication. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:37-44 [Conf]
  4. Zhonghai Lu, Mingchen Zhong, Axel Jantsch
    Evaluation of on-chip networks using deflection routing. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:296-301 [Conf]
  5. Ingo Sander, Axel Jantsch, Zhonghai Lu
    A Case Study of Hardware and Software Synthesis in ForSyDe. [Citation Graph (0, 0)][DBLP]
    ISSS, 2002, pp:86-91 [Conf]
  6. Zhonghai Lu, Bei Yin, Axel Jantsch
    Connection-oriented Multicasting in Wormhole-switched Networks on Chip. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:205-2110 [Conf]
  7. Zhonghai Lu, Axel Jantsch
    Traffic Configuration for Evaluating Networks on Chips. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2005, pp:535-540 [Conf]
  8. Zhonghai Lu, Ming Liu, Axel Jantsch
    Layered Switching for Networks on Chip. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:122-127 [Conf]
  9. Zhonghai Lu, Jonas Sicking, Ingo Sander, Axel Jantsch
    Using Synchronizers for Refining Synchronous Communication onto Hardware/Software Architectures. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2007, pp:143-149 [Conf]

  10. Analysis of communication delay bounds for network on chips. [Citation Graph (, )][DBLP]


  11. Applying network calculus for performance analysis of self-similar traffic in on-chip networks. [Citation Graph (, )][DBLP]


  12. Flow regulation for on-chip communication. [Citation Graph (, )][DBLP]


  13. Supporting Distributed Shared Memory on multi-core Network-on-Chips using a dual microcoded controller. [Citation Graph (, )][DBLP]


  14. FPGA-based adaptive computing for correlated multi-stream processing. [Citation Graph (, )][DBLP]


  15. Optimal regulation of traffic flows in networks-on-chip. [Citation Graph (, )][DBLP]


  16. Cluster-based Simulated Annealing for Mapping Cores onto 2D Mesh Networks on Chip. [Citation Graph (, )][DBLP]


  17. System-on-an-FPGA Design for Real-time Particle Track Recognition and Reconstruction in Physics Experiments. [Citation Graph (, )][DBLP]


  18. Exploration of Slot Allocation for On-Chip TDM Virtual Circuits. [Citation Graph (, )][DBLP]


  19. ATCA-based computation platform for data acquisition and triggering in particle physics experiments. [Citation Graph (, )][DBLP]


  20. Run-time Partial Reconfiguration speed investigation and architectural design space exploration. [Citation Graph (, )][DBLP]


  21. Slot allocation using logical networks for TDM virtual-circuit configuration for network-on-chip. [Citation Graph (, )][DBLP]


  22. From 2D to 3D NoCs: A case study on worst-case communication performance. [Citation Graph (, )][DBLP]


  23. Analytical Evaluation of Retransmission Schemes in Wireless Sensor Networks. [Citation Graph (, )][DBLP]


  24. Analysis of worst-case delay bounds for best-effort communication in wormhole networks on chip. [Citation Graph (, )][DBLP]


  25. Scalability of network-on-chip communication architecture for 3-D meshes. [Citation Graph (, )][DBLP]


  26. Traffic Splitting with Network Calculus for Mesh Sensor Networks. [Citation Graph (, )][DBLP]


  27. Refinement of Perfectly Synchronous Communication Model. [Citation Graph (, )][DBLP]


  28. A Reconfigurable Design Framework for FPGA Adaptive Computing. [Citation Graph (, )][DBLP]


  29. 3-D memory organization and performance analysis for multi-processor network-on-chip architecture. [Citation Graph (, )][DBLP]


  30. Physical mapping and performance study of a multi-clock 3-Dimensional Network-on-Chip mesh. [Citation Graph (, )][DBLP]


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