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Ingo Sander: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Zhonghai Lu, Axel Jantsch, Ingo Sander
    Feasibility analysis of messages for on-chip networks using wormhole routing. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:960-964 [Conf]
  2. Axel Jantsch, Ingo Sander
    On the roles of functions and objects in system specification. [Citation Graph (0, 0)][DBLP]
    CODES, 2000, pp:8-12 [Conf]
  3. Axel Jantsch, Ingo Sander, Wenbiao Wu
    The usage of stochastic processes in embedded system specifications. [Citation Graph (0, 0)][DBLP]
    CODES, 2001, pp:5-10 [Conf]
  4. Tarvo Raudvere, Ingo Sander, Ashish Kumar Singh, Axel Jantsch
    Verification of design decisions in ForSyDe. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2003, pp:176-181 [Conf]
  5. Ingo Sander, Axel Jantsch
    System synthesis utilizing a layered functional model. [Citation Graph (0, 0)][DBLP]
    CODES, 1999, pp:136-140 [Conf]
  6. Ingo Sander, Axel Jantsch
    Transformation based communication and clock domain refinement for system design. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:281-286 [Conf]
  7. Tarvo Raudvere, Ashish Kumar Singh, Ingo Sander, Axel Jantsch
    Polynomial Abstraction for Verification of Sequentially Implemented Combinational Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:690-691 [Conf]
  8. Ingo Sander, Axel Jantsch, Zhonghai Lu
    Development and Application of Design Transformations in ForSyDe. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10364-10369 [Conf]
  9. Zhonghai Lu, Ingo Sander, Axel Jantsch
    Towards Performance-Oriented Pattern-Based Refinement of Synchronous Models onto NoC Communication. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:37-44 [Conf]
  10. Rikard Thid, Ingo Sander, Axel Jantsch
    Flexible Bus and NoC Performance Analysis with Configurable Synthetic Workloads. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:681-688 [Conf]
  11. Tarvo Raudvere, Ingo Sander, Axel Jantsch
    A synchronization algorithm for local temporal refinements in perfectly synchronous models with nested feedback loops. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:353-358 [Conf]
  12. Tarvo Raudvere, Ashish Kumar Singh, Ingo Sander, Axel Jantsch
    System level verification of digital signal processing applications based on the polynomial abstraction technique. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:285-290 [Conf]
  13. Ingo Sander, Axel Jantsch, Zhonghai Lu
    A Case Study of Hardware and Software Synthesis in ForSyDe. [Citation Graph (0, 0)][DBLP]
    ISSS, 2002, pp:86-91 [Conf]
  14. Ingo Sander, Axel Jantsch
    Formal System Design Based on the Synchrony Hypothesis, Functional Models and Skeletons. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:318-323 [Conf]
  15. Ingo Sander, Axel Jantsch
    System modeling and transformational design refinement in ForSyDe [formal system design]. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:1, pp:17-32 [Journal]
  16. Zhonghai Lu, Jonas Sicking, Ingo Sander, Axel Jantsch
    Using Synchronizers for Refining Synchronous Communication onto Hardware/Software Architectures. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2007, pp:143-149 [Conf]

  17. Synchronization after design refinements with sensitive delay elements. [Citation Graph (, )][DBLP]

  18. Buffer minimization of real-time streaming applications scheduling on hybrid CPU/FPGA architectures. [Citation Graph (, )][DBLP]

  19. Pareto efficient design for reconfigurable streaming applications on CPU/FPGAs. [Citation Graph (, )][DBLP]

  20. Predicting energy and performance overhead of Real-Time Operating Systems. [Citation Graph (, )][DBLP]

  21. Energy efficient streaming applications with guaranteed throughput on MPSoCs. [Citation Graph (, )][DBLP]

  22. Performance analysis of reconfiguration in adaptive real-time streaming applications. [Citation Graph (, )][DBLP]

  23. The ANDRES Project: Analysis and Design of Run-Time Reconfigurable, Heterogeneous Systems. [Citation Graph (, )][DBLP]

  24. High-level estimation and trade-off analysis for adaptive real-time systems. [Citation Graph (, )][DBLP]

  25. Refinement of Perfectly Synchronous Communication Model. [Citation Graph (, )][DBLP]

  26. Modelling Adaptive Systems in ForSyDe. [Citation Graph (, )][DBLP]

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