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Rung-Bin Lin: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Rung-Bin Lin, Jinq-Chang Chen
    Low Power CMOS Off-Chip Drivers with Slew-rate Difference. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1999, pp:169-172 [Conf]
  2. Rung-Bin Lin, Isaac Shuo-Hsiu Chou, Chi-Ming Tsai
    Benchmark Circuits Improve the Quality of a Standard Cell Library. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1999, pp:173-176 [Conf]
  3. Rung-Bin Lin, Chi-Ming Tsai
    Weight-Based Bus-Invert Coding for Low-Power Applications. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:121-125 [Conf]
  4. Rung-Bin Lin, Meng-Chiou Wu, Wei-Chiu Tseng, Ming-Hsine Kuo, Tsai-Ying Lin, Shr-Cheng Tsai
    Design space exploration for minimizing multi-project wafer production cost. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:783-788 [Conf]
  5. Chi-Ming Tsai, Kun-Tien Kuo, Chyi-Hui Hong, Rung-Bin Lin
    An Adaptive Interconnect-Length Driven Placer. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:393-398 [Conf]
  6. Rung-Bin Lin, Eugene Shragowitz
    Fuzzy Logic Approach to Placement Problem. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:153-158 [Conf]
  7. Rung-Bin Lin, Da-Wei Hsu, Ming-Hsine Kuo, Meng-Chiou Wu
    Reticle Exposure Plans for Multi-Project Wafers. [Citation Graph (0, 0)][DBLP]
    DDECS, 2007, pp:341-344 [Conf]
  8. Meng-Chiou Wu, Rung-Bin Lin
    Reticle floorplanning of flexible chips for multi-project wafers. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2005, pp:494-497 [Conf]
  9. Guang-Wan Liao, Ja-Shong Feng, Rung-Bin Lin
    A divide-and-conquer approach to estimating minimum/maximum leakage current. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4717-4720 [Conf]
  10. Rung-Bin Lin
    Coupling reduction analysis of bus-invert coding. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5862-5865 [Conf]
  11. Rung-Bin Lin, Shuyu Chen
    Multi-layer constrained via minimization with conjugate conflict continuation graphs. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2004, pp:525-528 [Conf]
  12. Meng-Chiou Wu, Rung-Bin Lin
    Multiple project wafers for medium-volume IC production. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4725-4728 [Conf]
  13. Meng-Chiou Wu, Rung-Bin Lin
    Reticle Floorplanning and Wafer Dicing for Multiple Project Wafers. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:610-615 [Conf]
  14. Meng-Chiou Wu, Rung-Bin Lin
    A Comparative Study on Dicing of Multiple Project Wafers. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2005, pp:314-315 [Conf]
  15. Habib Youssef, Rung-Bin Lin, Eugene Shragowitz
    Bounds on Net Delays for Physical Design of Fast Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI, 1991, pp:111-118 [Conf]
  16. Rung-Bin Lin, Chi-Ming Tsai
    Weight-Based Bus-Invert Coding for Low-Power Applications. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:121-125 [Conf]
  17. Rung-Bin Lin, Meng-Chiou Wu
    A New Statistical Approach to Timing Analysis of VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1998, pp:507-0 [Conf]
  18. Chi-Ming Tsai, Kun-Tien Kuo, Chyi-Hui Hong, Rung-Bin Lin
    An Adaptive Interconnect-Length Driven Placer. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:393-398 [Conf]
  19. Chi-Ming Tsai, Guang-Wan Liao, Rung-Bin Lin
    A Low Power-Delay Product Page-Based Address Bus Coding Method. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:521-526 [Conf]
  20. Rung-Bin Lin
    Comments on "Filling algorithms and analyses for layout density control". [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:10, pp:1209-1211 [Journal]
  21. Suphachai Sutanthavibul, Eugene Shragowitz, Rung-Bin Lin
    An adaptive timing-driven placement for high performance VLSIs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:10, pp:1488-1498 [Journal]
  22. Tsai-Ying Lin, Tsung-Han Lin, Hui-Hsiang Tung, Rung-Bin Lin
    Double-via-driven standard cell library design. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:1212-1217 [Conf]
  23. Hsun-Chieh Yu, Rung-Bin Lin
    Is more redundancy better for on-chip bus encoding. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  24. Rung-Bin Lin, Shuyu Chen
    Conjugate conflict continuation graphs for multi-layer constrained via minimization. [Citation Graph (0, 0)][DBLP]
    Inf. Sci., 2007, v:177, n:12, pp:2436-2447 [Journal]
  25. Eric Q. Kang, Rung-Bin Lin, Eugene Shragowitz
    Fuzzy logic approach to VLSI placement. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1994, v:2, n:4, pp:489-501 [Journal]
  26. Rung-Bin Lin, Chi-Ming Tsai
    Theoretical analysis of bus-invert coding. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:6, pp:929-934 [Journal]

  27. A Multi-dimensional Pattern Run-Length Method for Test Data Compression. [Citation Graph (, )][DBLP]


  28. Deterministic Built-In Self-Test Using Multiple Linear Feedback Shift Registers for Low-Power Scan Testing. [Citation Graph (, )][DBLP]


  29. Power gating design for standard-cell-like structured ASICs. [Citation Graph (, )][DBLP]


  30. Via configurable three-input lookup-tables for structured ASICs. [Citation Graph (, )][DBLP]


  31. Router and cell library co-development for improving redundant via insertion at pins. [Citation Graph (, )][DBLP]


  32. Clock routing for structured ASICs with via-configurable fabrics. [Citation Graph (, )][DBLP]


  33. Standard Cell Like Via-Configurable Logic Block for Structured ASICs. [Citation Graph (, )][DBLP]


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