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Rung-Bin Lin :
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Rung-Bin Lin , Jinq-Chang Chen Low Power CMOS Off-Chip Drivers with Slew-rate Difference. [Citation Graph (0, 0)][DBLP ] ASP-DAC, 1999, pp:169-172 [Conf ] Rung-Bin Lin , Isaac Shuo-Hsiu Chou , Chi-Ming Tsai Benchmark Circuits Improve the Quality of a Standard Cell Library. [Citation Graph (0, 0)][DBLP ] ASP-DAC, 1999, pp:173-176 [Conf ] Rung-Bin Lin , Chi-Ming Tsai Weight-Based Bus-Invert Coding for Low-Power Applications. [Citation Graph (0, 0)][DBLP ] ASP-DAC, 2002, pp:121-125 [Conf ] Rung-Bin Lin , Meng-Chiou Wu , Wei-Chiu Tseng , Ming-Hsine Kuo , Tsai-Ying Lin , Shr-Cheng Tsai Design space exploration for minimizing multi-project wafer production cost. [Citation Graph (0, 0)][DBLP ] ASP-DAC, 2006, pp:783-788 [Conf ] Chi-Ming Tsai , Kun-Tien Kuo , Chyi-Hui Hong , Rung-Bin Lin An Adaptive Interconnect-Length Driven Placer. [Citation Graph (0, 0)][DBLP ] ASP-DAC, 2002, pp:393-398 [Conf ] Rung-Bin Lin , Eugene Shragowitz Fuzzy Logic Approach to Placement Problem. [Citation Graph (0, 0)][DBLP ] DAC, 1992, pp:153-158 [Conf ] Rung-Bin Lin , Da-Wei Hsu , Ming-Hsine Kuo , Meng-Chiou Wu Reticle Exposure Plans for Multi-Project Wafers. [Citation Graph (0, 0)][DBLP ] DDECS, 2007, pp:341-344 [Conf ] Meng-Chiou Wu , Rung-Bin Lin Reticle floorplanning of flexible chips for multi-project wafers. [Citation Graph (0, 0)][DBLP ] ACM Great Lakes Symposium on VLSI, 2005, pp:494-497 [Conf ] Guang-Wan Liao , Ja-Shong Feng , Rung-Bin Lin A divide-and-conquer approach to estimating minimum/maximum leakage current. [Citation Graph (0, 0)][DBLP ] ISCAS (5), 2005, pp:4717-4720 [Conf ] Rung-Bin Lin Coupling reduction analysis of bus-invert coding. [Citation Graph (0, 0)][DBLP ] ISCAS (6), 2005, pp:5862-5865 [Conf ] Rung-Bin Lin , Shuyu Chen Multi-layer constrained via minimization with conjugate conflict continuation graphs. [Citation Graph (0, 0)][DBLP ] ISCAS (4), 2004, pp:525-528 [Conf ] Meng-Chiou Wu , Rung-Bin Lin Multiple project wafers for medium-volume IC production. [Citation Graph (0, 0)][DBLP ] ISCAS (5), 2005, pp:4725-4728 [Conf ] Meng-Chiou Wu , Rung-Bin Lin Reticle Floorplanning and Wafer Dicing for Multiple Project Wafers. [Citation Graph (0, 0)][DBLP ] ISQED, 2005, pp:610-615 [Conf ] Meng-Chiou Wu , Rung-Bin Lin A Comparative Study on Dicing of Multiple Project Wafers. [Citation Graph (0, 0)][DBLP ] ISVLSI, 2005, pp:314-315 [Conf ] Habib Youssef , Rung-Bin Lin , Eugene Shragowitz Bounds on Net Delays for Physical Design of Fast Circuits. [Citation Graph (0, 0)][DBLP ] VLSI, 1991, pp:111-118 [Conf ] Rung-Bin Lin , Chi-Ming Tsai Weight-Based Bus-Invert Coding for Low-Power Applications. [Citation Graph (0, 0)][DBLP ] VLSI Design, 2002, pp:121-125 [Conf ] Rung-Bin Lin , Meng-Chiou Wu A New Statistical Approach to Timing Analysis of VLSI Circuits. [Citation Graph (0, 0)][DBLP ] VLSI Design, 1998, pp:507-0 [Conf ] Chi-Ming Tsai , Kun-Tien Kuo , Chyi-Hui Hong , Rung-Bin Lin An Adaptive Interconnect-Length Driven Placer. [Citation Graph (0, 0)][DBLP ] VLSI Design, 2002, pp:393-398 [Conf ] Chi-Ming Tsai , Guang-Wan Liao , Rung-Bin Lin A Low Power-Delay Product Page-Based Address Bus Coding Method. [Citation Graph (0, 0)][DBLP ] VLSI Design, 2003, pp:521-526 [Conf ] Rung-Bin Lin Comments on "Filling algorithms and analyses for layout density control". [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:10, pp:1209-1211 [Journal ] Suphachai Sutanthavibul , Eugene Shragowitz , Rung-Bin Lin An adaptive timing-driven placement for high performance VLSIs. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:10, pp:1488-1498 [Journal ] Tsai-Ying Lin , Tsung-Han Lin , Hui-Hsiang Tung , Rung-Bin Lin Double-via-driven standard cell library design. [Citation Graph (0, 0)][DBLP ] DATE, 2007, pp:1212-1217 [Conf ] Hsun-Chieh Yu , Rung-Bin Lin Is more redundancy better for on-chip bus encoding. [Citation Graph (0, 0)][DBLP ] ISCAS, 2006, pp:- [Conf ] Rung-Bin Lin , Shuyu Chen Conjugate conflict continuation graphs for multi-layer constrained via minimization. [Citation Graph (0, 0)][DBLP ] Inf. Sci., 2007, v:177, n:12, pp:2436-2447 [Journal ] Eric Q. Kang , Rung-Bin Lin , Eugene Shragowitz Fuzzy logic approach to VLSI placement. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 1994, v:2, n:4, pp:489-501 [Journal ] Rung-Bin Lin , Chi-Ming Tsai Theoretical analysis of bus-invert coding. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2002, v:10, n:6, pp:929-934 [Journal ] A Multi-dimensional Pattern Run-Length Method for Test Data Compression. [Citation Graph (, )][DBLP ] Deterministic Built-In Self-Test Using Multiple Linear Feedback Shift Registers for Low-Power Scan Testing. [Citation Graph (, )][DBLP ] Power gating design for standard-cell-like structured ASICs. [Citation Graph (, )][DBLP ] Via configurable three-input lookup-tables for structured ASICs. [Citation Graph (, )][DBLP ] Router and cell library co-development for improving redundant via insertion at pins. [Citation Graph (, )][DBLP ] Clock routing for structured ASICs with via-configurable fabrics. [Citation Graph (, )][DBLP ] Standard Cell Like Via-Configurable Logic Block for Structured ASICs. [Citation Graph (, )][DBLP ] Search in 0.002secs, Finished in 0.332secs