Search the dblp DataBase

Publications of Author

1. Chih-Chang Lin, David Ihsin Cheng, Malgorzata Marek-Sadowska, Kuang-Chien Chen
   Logic rectification and synthesis for engineering change. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 1995, pp:- [Conf]
   
2. Chih-Chang Lin, Kuang-Chien Chen, Shih-Chieh Chang, Malgorzata Marek-Sadowska, Kwang-Ting Cheng
   Logic Synthesis for Engineering Change. [Citation Graph (0, 0)][DBLP]
   DAC, 1995, pp:647-652 [Conf]
   
3. Chih-Chang Lin, Malgorzata Marek-Sadowska, Kwang-Ting Cheng, Mike Tien-Chien Lee
   Test Point Insertion: Scan Paths through Combinational Logic. [Citation Graph (0, 0)][DBLP]
   DAC, 1996, pp:268-273 [Conf]
   
4. Peichen Pan, Chih-Chang Lin
   A New Retiming-Based Technology Mapping Algorithm for LUT-based FPGAs. [Citation Graph (0, 0)][DBLP]
   FPGA, 1998, pp:35-42 [Conf]
   
5. David Ihsin Cheng, Chih-Chang Lin, Malgorzata Marek-Sadowska
   Circuit partitioning with logic perturbation. [Citation Graph (0, 0)][DBLP]
   ICCAD, 1995, pp:650-655 [Conf]
   
6. Chih-Chang Lin, Mike Tien-Chien Lee, Malgorzata Marek-Sadowska, Kuang-Chien Chen
   Cost-free scan: a low-overhead scan path design methodology. [Citation Graph (0, 0)][DBLP]
   ICCAD, 1995, pp:528-533 [Conf]
   
7. Chih-Chang Lin, Malgorzata Marek-Sadowska, Duane Gatlin
   Universal logic gate for FPGA design. [Citation Graph (0, 0)][DBLP]
   ICCAD, 1994, pp:164-168 [Conf]
   
8. Chih-Chang Lin, Kuang-Chien Chen, Malgorzata Marek-Sadowska
   Logic synthesis for engineering change. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:3, pp:282-292 [Journal]
   
9. Chih-Chang Lin, Malgorzata Marek-Sadowska
   On designing universal logic blocks and their application to FPGA design. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:5, pp:519-527 [Journal]
   
10. Chih-Chang Lin, Malgorzata Marek-Sadowska, Kwang-Ting Cheng, Mike Tien-Chien Lee
    Test-point insertion: scan paths through functional logic. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:9, pp:838-851 [Journal]
    
11. Chih-Chang Lin, Malgorzata Marek-Sadowska, Mike Tien-Chien Lee, Kuang-Chien Chen
    Cost-free scan: a low-overhead scan path design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:9, pp:852-861 [Journal]