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Publications of Author

1. Chih-Chang Lin, David Ihsin Cheng, Malgorzata Marek-Sadowska, Kuang-Chien Chen
   Logic rectification and synthesis for engineering change. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 1995, pp:- [Conf]
   
2. Yu-Liang Wu, Xiao-Long Yuan, David Ihsin Cheng
   Circuit partitioning with coupled logic restructuring techniques. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2000, pp:655-660 [Conf]
   
3. Shih-Chieh Chang, David Ihsin Cheng
   Efficient Boolean Division and Substitution. [Citation Graph (0, 0)][DBLP]
   DAC, 1998, pp:342-347 [Conf]
   
4. David Ihsin Cheng, Kwang-Ting Cheng, Deborah C. Wang, Malgorzata Marek-Sadowska
   A New Hybrid Methodology for Power Estimation. [Citation Graph (0, 0)][DBLP]
   DAC, 1996, pp:439-444 [Conf]
   
5. Andreas Kuehlmann, David Ihsin Cheng, Arvind Srinivasan, David P. LaPotin
   Error Diagnosis for Transistor-Level Verification. [Citation Graph (0, 0)][DBLP]
   DAC, 1994, pp:218-224 [Conf]
   
6. David Ihsin Cheng
   On Removing Multiple Redundancies in Combinational Circuits. [Citation Graph (0, 0)][DBLP]
   DATE, 1998, pp:738-742 [Conf]
   
7. Chak-Chung Cheung, Yu-Liang Wu, David Ihsin Cheng
   Further improve circuit partitioning using GBAW logic perturbation techniques. [Citation Graph (0, 0)][DBLP]
   DATE, 2001, pp:233-239 [Conf]
   
8. Shih-Chieh Chang, David Ihsin Cheng, Malgorzata Marek-Sadowska
   Minimizing ROBDD Size of Incompletely Specified Multiple Output Functions. [Citation Graph (0, 0)][DBLP]
   EDAC-ETC-EUROASIC, 1994, pp:620-624 [Conf]
   
9. David Ihsin Cheng, Chih-Chang Lin, Malgorzata Marek-Sadowska
   Circuit partitioning with logic perturbation. [Citation Graph (0, 0)][DBLP]
   ICCAD, 1995, pp:650-655 [Conf]
   
10. Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, David Ihsin Cheng
    Error Tracer: A Fault-Simualtion-Based Approach to Design Error Diagnosis. [Citation Graph (0, 0)][DBLP]
    ITC, 1997, pp:974-981 [Conf]
    
11. Shih-Chieh Chang, David Ihsin Cheng
    Efficient Boolean division and substitution using redundancy addition and removing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:8, pp:1096-1106 [Journal]
    
12. David Ihsin Cheng, Kwang-Ting Cheng, Deborah C. Wang, Malgorzata Marek-Sadowska
    A hybrid methodology for switching activities estimation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:4, pp:357-366 [Journal]
    
13. Yu-Liang Wu, Chak-Chung Cheung, David Ihsin Cheng, Hongbing Fan
    Further improve circuit partitioning using GBAW logic perturbation techniques. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:3, pp:451-460 [Journal]