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Malgorzata Marek-Sadowska: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Chih-Chang Lin, David Ihsin Cheng, Malgorzata Marek-Sadowska, Kuang-Chien Chen
    Logic rectification and synthesis for engineering change. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1995, pp:- [Conf]
  2. Yu-Liang Wu, Malgorzata Marek-Sadowska
    Routing on regular segmented 2-D FPGAs. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1995, pp:- [Conf]
  3. Tong Xiao, Malgorzata Marek-Sadowska
    Crosstalk Reduction by Transistor Sizing. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1999, pp:137-140 [Conf]
  4. Bo Hu, Malgorzata Marek-Sadowska
    Wire length prediction based clustering and its application in placement. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:800-805 [Conf]
  5. Donald Chai, Alex Kondratyev, Yajun Ran, Kenneth H. Tseng, Yosinori Watanabe, Malgorzata Marek-Sadowska
    Temporofunctional crosstalk noise analysis. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:860-863 [Conf]
  6. Chih-Wei Jim Chang, Chung-Kuan Cheng, Peter Suaris, Malgorzata Marek-Sadowska
    Fast post-placement rewiring using easily detectable functional symmetries. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:286-289 [Conf]
  7. Shih-Chieh Chang, Kwang-Ting Cheng, Nam Sung Woo, Malgorzata Marek-Sadowska
    Layout Driven Logic Synthesis for FPGAs. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:308-313 [Conf]
  8. Douglas Chang, Mike Tien-Chien Lee, Malgorzata Marek-Sadowska, Takashi Aikyo, Kwang-Ting Cheng
    A Test Synthesis Approach to Reducing BALLAST DFT Overhead. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:466-471 [Conf]
  9. Shih-Chieh Chang, Malgorzata Marek-Sadowska, Kwang-Ting Cheng
    An Efficient Algorithm for Local Don't Care Sets Calculation. [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:663-667 [Conf]
  10. Chih-Wei Jim Chang, Kai Wang, Malgorzata Marek-Sadowska
    Layout-Driven Hot-Carrier Degradation Minimization Using Logic Restructuring Techniques. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:97-102 [Conf]
  11. Lauren Hui Chen, Malgorzata Marek-Sadowska, Forrest Brewer
    Coping with buffer delay change due to power and ground noise. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:860-865 [Conf]
  12. David Ihsin Cheng, Kwang-Ting Cheng, Deborah C. Wang, Malgorzata Marek-Sadowska
    A New Hybrid Methodology for Power Estimation. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:439-444 [Conf]
  13. Rajiv Dutta, Malgorzata Marek-Sadowska
    Automatic Sizing of Power/Ground (P/G) Networks in VLSI. [Citation Graph (0, 0)][DBLP]
    DAC, 1989, pp:783-786 [Conf]
  14. Bo Hu, Yosinori Watanabe, Alex Kondratyev, Malgorzata Marek-Sadowska
    Gain-based technology mapping for discrete-size cell libraries. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:574-579 [Conf]
  15. Yi-Min Jiang, Angela Krstic, Kwang-Ting Cheng, Malgorzata Marek-Sadowska
    Post-Layout Logic Restructuring for Performance Optimization. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:662-665 [Conf]
  16. Chih-Chang Lin, Kuang-Chien Chen, Shih-Chieh Chang, Malgorzata Marek-Sadowska, Kwang-Ting Cheng
    Logic Synthesis for Engineering Change. [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:647-652 [Conf]
  17. Chih-Chang Lin, Malgorzata Marek-Sadowska, Kwang-Ting Cheng, Mike Tien-Chien Lee
    Test Point Insertion: Scan Paths through Combinational Logic. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:268-273 [Conf]
  18. Shen Lin, Malgorzata Marek-Sadowska, Ernest S. Kuh
    Delay and Area Optimization in Standard-Cell Design. [Citation Graph (0, 0)][DBLP]
    DAC, 1990, pp:349-352 [Conf]
  19. Luca Macchiarulo, Malgorzata Marek-Sadowska
    Wave-steering one-hot encoded FSMs. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:357-360 [Conf]
  20. Qinghua Liu, Malgorzata Marek-Sadowska
    Pre-layout wire length and congestion estimation. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:582-587 [Conf]
  21. Arindam Mukherjee, Ranganathan Sudhakar, Malgorzata Marek-Sadowska, Stephen I. Long
    Wave Steering in YADDs: A Novel Non-Iterative Synthesis and Layout Technique. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:466-471 [Conf]
  22. Yu-Liang Wu, Malgorzata Marek-Sadowska
    Orthogonal Greedy Coupling - A New Optimization Approach to 2-D FPGA Routing. [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:568-573 [Conf]
  23. Yajun Ran, Malgorzata Marek-Sadowska
    Crosstalk noise in FPGAs. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:944-949 [Conf]
  24. Yajun Ran, Malgorzata Marek-Sadowska
    On designing via-configurable cell blocks for regular fabrics. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:198-203 [Conf]
  25. Amit Singh, Arindam Mukherjee, Malgorzata Marek-Sadowska
    Latency and Latch Count Minimization in Wave Steered Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:383-388 [Conf]
  26. Kun-Han Tsai, Sybille Hellebrand, Janusz Rajski, Malgorzata Marek-Sadowska
    STARBIST: Scan Autocorrelated Random Pattern Generation. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:472-477 [Conf]
  27. Chien-Chung Tsai, Malgorzata Marek-Sadowska
    Boolean Matching Using Generalized Reed-Muller Forms. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:339-344 [Conf]
  28. Chien-Chung Tsai, Malgorzata Marek-Sadowska
    Multilevel Logic Synthesis for Arithmetic Functions. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:242-247 [Conf]
  29. Ashok Vittal, Malgorzata Marek-Sadowska
    Minimal Delay Interconnect Design Using Alphabetic Trees. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:392-396 [Conf]
  30. Ashok Vittal, Malgorzata Marek-Sadowska
    Power Optimal Buffered Clock Tree Design. [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:497-502 [Conf]
  31. Ashok Vittal, Malgorzata Marek-Sadowska
    Power Distribution Topology Design. [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:503-507 [Conf]
  32. Kai Wang, Malgorzata Marek-Sadowska
    On-chip power supply network optimization using multigrid-based technique. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:113-118 [Conf]
  33. Kai Wang, Malgorzata Marek-Sadowska
    Buffer sizing for clock power minimization subject to general skew constraints. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:159-164 [Conf]
  34. Tong Xiao, Malgorzata Marek-Sadowska
    Functional Correlation Analysis in Crosstalk Induced Critical Paths Identification. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:653-656 [Conf]
  35. Chao-Yang Yeh, Malgorzata Marek-Sadowska
    Delay budgeting in sequential circuit with application on FPGA placement. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:202-207 [Conf]
  36. Malgorzata Marek-Sadowska
    Two-dimensional router for double layer layout. [Citation Graph (0, 0)][DBLP]
    DAC, 1985, pp:117-123 [Conf]
  37. Douglas Chang, Kwang-Ting Cheng, Malgorzata Marek-Sadowska, Mike Tien-Chien Lee
    Functional Scan Chain Testing. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:278-0 [Conf]
  38. Chih-Wei Jim Chang, Bo Hu, Malgorzata Marek-Sadowska
    In-place delay constrained power optimization using functional symmetries. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:377-382 [Conf]
  39. Lauren Hui Chen, Malgorzata Marek-Sadowska
    Closed-Form Crosstalk Noise Metrics for Physical Design Applications. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:812-819 [Conf]
  40. Luca Macchiarulo, Shih-Ming Shu, Malgorzata Marek-Sadowska
    Wave Steered FSMs. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:270-276 [Conf]
  41. Arindam Mukherjee, Kai Wang, Lauren Hui Chen, Malgorzata Marek-Sadowska
    Sizing Power/Ground Meshes for Clocking and Computing Circuit Components. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:176-185 [Conf]
  42. Yajun Ran, Alex Kondratyev, Yosinori Watanabe, Malgorzata Marek-Sadowska
    Eliminating False Positives in Crosstalk Noise Analysis. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1192-1197 [Conf]
  43. Kai Wang, Malgorzata Marek-Sadowska
    Power/Ground Mesh Area Optimization Using Multigrid-Based Technique. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10850-10855 [Conf]
  44. Nobuo Funabiki, Amit Singh, Arindam Mukherjee, Malgorzata Marek-Sadowska
    A Global Routing Technique for Wave-Steering Design Methodology. [Citation Graph (0, 0)][DBLP]
    DSD, 2001, pp:430-437 [Conf]
  45. Shih-Chieh Chang, David Ihsin Cheng, Malgorzata Marek-Sadowska
    Minimizing ROBDD Size of Incompletely Specified Multiple Output Functions. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:620-624 [Conf]
  46. Yu-Liang Wu, Malgorzata Marek-Sadowska
    An Efficient Router for 2-D Field Programmable Gate Arrays. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:412-416 [Conf]
  47. Douglas Chang, Malgorzata Marek-Sadowska
    Buffer Minimization and Time-Multiplexed I/O on Dynamically Reconfigurable FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 1997, pp:142-148 [Conf]
  48. Douglas Chang, Malgorzata Marek-Sadowska
    Partitioning Sequential Circuits on Dynamically Reconfiguable FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 1998, pp:161-167 [Conf]
  49. Amit Singh, Malgorzata Marek-Sadowska
    Efficient circuit clustering for area and power reduction in FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 2002, pp:59-66 [Conf]
  50. Amit Singh, Arindam Mukherjee, Malgorzata Marek-Sadowska
    Interconnect pipelining in a throughput-intensive FPGA architecture. [Citation Graph (0, 0)][DBLP]
    FPGA, 2001, pp:153-160 [Conf]
  51. Amit Singh, Luca Macchiarulo, Arindam Mukherjee, Malgorzata Marek-Sadowska
    A novel high throughput reconfigurable FPGA architecture. [Citation Graph (0, 0)][DBLP]
    FPGA, 2000, pp:22-29 [Conf]
  52. Chao-Yang Yeh, Malgorzata Marek-Sadowska
    Skew-programmable clock design for FPGA and skew-aware placement. [Citation Graph (0, 0)][DBLP]
    FPGA, 2005, pp:33-40 [Conf]
  53. Chih-Wei Jim Chang, Malgorzata Marek-Sadowska
    Who are the alternative wires in your neighborhood? (alternative wires identification without search). [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2001, pp:103-108 [Conf]
  54. Hailin Jiang, Kai Wang, Malgorzata Marek-Sadowska
    Clock skew bounds estimation under power supply and process variations. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2005, pp:332-336 [Conf]
  55. Qinghua Liu, Malgorzata Marek-Sadowska
    A congestion-driven placement framework with local congestion prediction. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2005, pp:488-493 [Conf]
  56. Chien-Chung Tsai, Malgorzata Marek-Sadowska
    Logic Synthesis for Testability. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1996, pp:118-121 [Conf]
  57. Bo Hu, Malgorzata Marek-Sadowska
    Multilevel expansion-based VLSI placement with blockages. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:558-564 [Conf]
  58. Bo Hu, Malgorzata Marek-Sadowska
    Congestion minimization during placement without estimation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:739-745 [Conf]
  59. Shih-Chieh Chang, Lukas P. P. P. van Ginneken, Malgorzata Marek-Sadowska
    Fast Boolean optimization by rewiring. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1996, pp:262-269 [Conf]
  60. Chih-Wei Jim Chang, Malgorzata Marek-Sadowska
    Single-Pass Redundancy Addition and Removal. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:606-609 [Conf]
  61. Chih-Wei Jim Chang, Malgorzata Marek-Sadowska
    ATPG-based logic synthesis: an overview. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:786-789 [Conf]
  62. Shih-Chieh Chang, Malgorzata Marek-Sadowska
    Perturb and simplify: multi-level boolean network optimizer. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:2-5 [Conf]
  63. David Ihsin Cheng, Chih-Chang Lin, Malgorzata Marek-Sadowska
    Circuit partitioning with logic perturbation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:650-655 [Conf]
  64. Chih-Chang Lin, Mike Tien-Chien Lee, Malgorzata Marek-Sadowska, Kuang-Chien Chen
    Cost-free scan: a low-overhead scan path design methodology. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:528-533 [Conf]
  65. Chih-Chang Lin, Malgorzata Marek-Sadowska, Duane Gatlin
    Universal logic gate for FPGA design. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:164-168 [Conf]
  66. Malgorzata Marek-Sadowska, Majid Sarrafzadeh
    The Crossing Distribution Problem. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:528-531 [Conf]
  67. Massoud Pedram, Malgorzata Marek-Sadowska, Ernest S. Kuh
    Floorplanning with Pin Assignment. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1990, pp:98-101 [Conf]
  68. Yajun Ran, Malgorzata Marek-Sadowska
    An integrated design flow for a via-configurable gate array. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:582-589 [Conf]
  69. Yajun Ran, Malgorzata Marek-Sadowska
    Via-configurable routing architectures and fast design mappability estimation for regular fabrics. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:25-32 [Conf]
  70. Amit Singh, Ganapathy Parthasarathy, Malgorzata Marek-Sadowska
    Interconnect Resource-Aware Placement for Hierarchical FPGAs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:132-136 [Conf]
  71. Ashok Vittal, Hein Ha, Forrest Brewer, Malgorzata Marek-Sadowska
    Clock skew optimization for ground bounce control. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1996, pp:395-399 [Conf]
  72. Chao-Yang Yeh, Malgorzata Marek-Sadowska
    Minimum-Area Sequential Budgeting for FPGA. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:813-817 [Conf]
  73. Chao-Yang Yeh, Malgorzata Marek-Sadowska
    Timing-aware power noise reduction in layout. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:627-634 [Conf]
  74. Fillia Makedon, Malgorzata Marek-Sadowska
    Analysis of Heuristic Reasoning for the Visualization of CAD Quadratic. [Citation Graph (0, 0)][DBLP]
    ICCAL, 1989, pp:359-378 [Conf]
  75. Shih-Chieh Chang, Malgorzata Marek-Sadowska
    Technology Mapping via Transformations of Function Graphs. [Citation Graph (0, 0)][DBLP]
    ICCD, 1992, pp:159-162 [Conf]
  76. Hailin Jiang, Malgorzata Marek-Sadowska, Sani R. Nassif
    Benefits and Costs of Power-Gating Technique. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:559-566 [Conf]
  77. Qinghua Liu, Malgorzata Marek-Sadowska
    Pre-layout Physical Connectivity Prediction with Application in Clustering-Based Placement. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:31-37 [Conf]
  78. Yajun Ran, Malgorzata Marek-Sadowska
    The Magic of a Via-Configurable Regular Fabric. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:338-343 [Conf]
  79. Kai Wang, Malgorzata Marek-Sadowska
    Potential Slack Budgeting with Clock Skew Optimization. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:265-271 [Conf]
  80. Zhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski
    Multiple Fault Diagnosis Using n-Detection Tests. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:198-0 [Conf]
  81. Zhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski
    Diagnosis of Hold Time Defects. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:192-199 [Conf]
  82. Tong Xiao, Malgorzata Marek-Sadowska
    Worst Delay Estimation in Crosstalk Aware Static Timing Analysis. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:115-120 [Conf]
  83. Tong Xiao, Malgorzata Marek-Sadowska
    Gate Sizing to Eliminate Crosstalk Induced Timing Violation. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:186-191 [Conf]
  84. Ming-Fu Hsiao, Malgorzata Marek-Sadowska, Sao-Jie Chen
    A crosstalk aware two-pin net router. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:485-488 [Conf]
  85. Ming-Fu Hsiao, Malgorzata Marek-Sadowska, Sao-Jie Chen
    Minimizing coupling jitter by buffer resizing for coupled clock networks. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:509-512 [Conf]
  86. Chien-Chung Tsai, Malgorzata Marek-Sadowska
    Detecting Symmetric Variables in Boolean Functions using Generalized Reel-Muller Forms. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:287-290 [Conf]
  87. Stan Grygiel, Marek A. Perkowski, Malgorzata Marek-Sadowska, Tadeusz Luba, Lech Józwiak
    Cube Diagram Bundles: A New Representation of Strongly Unspecified Multiple-Valued Functions and Relations. [Citation Graph (0, 0)][DBLP]
    ISMVL, 1997, pp:287-292 [Conf]
  88. Marek A. Perkowski, Malgorzata Marek-Sadowska, Lech Józwiak, Tadeusz Luba, Stan Grygiel, Miroslawa Nowicka, Rahul Malvi, Zhi Wang, Jin S. Zhang
    Decomposition of Multiple-Valued Relations . [Citation Graph (0, 0)][DBLP]
    ISMVL, 1997, pp:13-18 [Conf]
  89. Lauren Hui Chen, Malgorzata Marek-Sadowska
    Incremental delay change due to crosstalk noise. [Citation Graph (0, 0)][DBLP]
    ISPD, 2002, pp:120-125 [Conf]
  90. Bo Hu, Hailin Jiang, Qinghua Liu, Malgorzata Marek-Sadowska
    Synthesis and placement flow for gain-based programmable regular fabrics. [Citation Graph (0, 0)][DBLP]
    ISPD, 2003, pp:197-203 [Conf]
  91. Bo Hu, Malgorzata Marek-Sadowska
    FAR: fixed-points addition & relaxation based placement. [Citation Graph (0, 0)][DBLP]
    ISPD, 2002, pp:161-166 [Conf]
  92. Bo Hu, Malgorzata Marek-Sadowska
    Fine granularity clustering for large scale placement problems. [Citation Graph (0, 0)][DBLP]
    ISPD, 2003, pp:67-74 [Conf]
  93. Lauren Hui Chen, Malgorzata Marek-Sadowska
    Aggressor alignment for worst-case coupling noise. [Citation Graph (0, 0)][DBLP]
    ISPD, 2000, pp:48-54 [Conf]
  94. Bo Hu, Yue Zeng, Malgorzata Marek-Sadowska
    mFAR: fixed-points-addition-based VLSI placement algorithm. [Citation Graph (0, 0)][DBLP]
    ISPD, 2005, pp:239-241 [Conf]
  95. Qinghua Liu, Malgorzata Marek-Sadowska
    A study of netlist structure and placement efficiency. [Citation Graph (0, 0)][DBLP]
    ISPD, 2004, pp:198-203 [Conf]
  96. Qinghua Liu, Malgorzata Marek-Sadowska
    Wire length prediction-based technology mapping and fanout optimization. [Citation Graph (0, 0)][DBLP]
    ISPD, 2005, pp:145-151 [Conf]
  97. Amit Singh, Malgorzata Marek-Sadowska
    Circuit clustering using graph coloring. [Citation Graph (0, 0)][DBLP]
    ISPD, 1999, pp:164-169 [Conf]
  98. Kai Wang, Malgorzata Marek-Sadowska
    Clock network sizing via sequential linear programming with time-domain analysis. [Citation Graph (0, 0)][DBLP]
    ISPD, 2004, pp:182-189 [Conf]
  99. Lauren Hui Chen, Malgorzata Marek-Sadowska
    Efficient Closed-Form Crosstalk Delay Metrics. [Citation Graph (0, 0)][DBLP]
    ISQED, 2002, pp:431-436 [Conf]
  100. Ming-Fu Hsiao, Malgorzata Marek-Sadowska, Sao-Jie Chen
    Minimizing Inter-Clock Coupling Jitter. [Citation Graph (0, 0)][DBLP]
    ISQED, 2003, pp:333-338 [Conf]
  101. Vishal J. Mehta, Malgorzata Marek-Sadowska, Zhiyuan Wang, Kun-Han Tsai, Janusz Rajski
    Delay Fault Diagnosis for Non-Robust Test. [Citation Graph (0, 0)][DBLP]
    ISQED, 2006, pp:463-472 [Conf]
  102. Tong Xiao, Malgorzata Marek-Sadowska
    Efficient Delay Calculation in Presence of Crosstalk. [Citation Graph (0, 0)][DBLP]
    ISQED, 2000, pp:491-498 [Conf]
  103. Chung-Kuan Tsai, Malgorzata Marek-Sadowska
    Modeling Crosstalk Induced Delay. [Citation Graph (0, 0)][DBLP]
    ISQED, 2003, pp:189-194 [Conf]
  104. Chung-Kuan Tsai, Malgorzata Marek-Sadowska
    An Interconnect Insensitive Linear Time-Varying Driver Model for Static Timing Analysis. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:654-661 [Conf]
  105. Chung-Kuan Tsai, Malgorzata Marek-Sadowska
    Analysis of Process Variation's Effect on SRAM's Read Stability. [Citation Graph (0, 0)][DBLP]
    ISQED, 2006, pp:603-610 [Conf]
  106. Zhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski
    Delay Fault Diagnosis Using Timing Information. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:485-490 [Conf]
  107. Hailin Jiang, Malgorzata Marek-Sadowska
    Power-Gating Aware Floorplanning. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:853-860 [Conf]
  108. Kun-Han Tsai, Malgorzata Marek-Sadowska, Janusz Rajski
    Scan-Encoded Test Pattern Generation for BIST. [Citation Graph (0, 0)][DBLP]
    ITC, 1997, pp:548-556 [Conf]
  109. Kuo-Hui Tsai, Tompson, Janusz Rajski, Malgorzata Marek-Sadowska
    STAR-ATPG: a high speed test pattern generator for large scan designs. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:1021-1030 [Conf]
  110. Zhiyuan Wang, Kun-Han Tsai, Malgorzata Marek-Sadowska, Janusz Rajski
    An Efficient and Effective Methodology on the Multiple Fault Diagnosis. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:329-338 [Conf]
  111. Ganapathy Parthasarathy, Malgorzata Marek-Sadowska, Arindam Mukherjee, Amit Singh
    Interconnect complexity-aware FPGA placement using Rent's rule. [Citation Graph (0, 0)][DBLP]
    SLIP, 2001, pp:115-121 [Conf]
  112. Amit Singh, Malgorzata Marek-Sadowska
    FPGA interconnect planning. [Citation Graph (0, 0)][DBLP]
    SLIP, 2002, pp:23-30 [Conf]
  113. Chao-Yang Yeh, Malgorzata Marek-Sadowska
    Sequential delay budgeting with interconnect prediction. [Citation Graph (0, 0)][DBLP]
    SLIP, 2003, pp:23-30 [Conf]
  114. Qinghua Liu, Bo Hu, Malgorzata Marek-Sadowska
    Wire length prediction in constraint driven placement. [Citation Graph (0, 0)][DBLP]
    SLIP, 2003, pp:99-105 [Conf]
  115. Ashok Vittal, Lauren Hui Chen, Malgorzata Marek-Sadowska, Kai-Ping Wang, Sherry Yang
    Modeling Crosstalk in Resistive VLSI Interconnections. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:470-475 [Conf]
  116. Arindam Mukherjee, Malgorzata Marek-Sadowska
    Clock and Power Gating with Timing Closure. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2003, v:20, n:3, pp:32-39 [Journal]
  117. Shih-Chieh Chang, Lukas P. P. P. van Ginneken, Malgorzata Marek-Sadowska
    Circuit Optimization by Rewiring. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1999, v:48, n:9, pp:962-970 [Journal]
  118. Douglas Chang, Malgorzata Marek-Sadowska
    Partitioning Sequential Circuits on Dynamically Reconfigurable FPGAs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1999, v:48, n:6, pp:565-578 [Journal]
  119. Luca Macchiarulo, Shih-Min Shu, Malgorzata Marek-Sadowska
    Pipelining Sequential Circuits with Wave Steering. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2004, v:53, n:9, pp:1205-1210 [Journal]
  120. Chien-Chung Tsai, Malgorzata Marek-Sadowska
    Generalized Reed-Muller Forms as a Tool to Detect Symmetries. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1996, v:45, n:1, pp:33-40 [Journal]
  121. Chien-Chung Tsai, Malgorzata Marek-Sadowska
    Boolean Functions Classification via Fixed Polarity Reed-Muller Forms. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1997, v:46, n:2, pp:173-186 [Journal]
  122. Yu-Liang Wu, Hongbing Fan, Malgorzata Marek-Sadowska, C. K. Wong
    OBDD Minimization Based on Two-Level Representation of Boolean Functions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2000, v:49, n:12, pp:1371-1379 [Journal]
  123. Bo Hu, Malgorzata Marek-Sadowska
    Fine granularity clustering-based placement. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:4, pp:527-536 [Journal]
  124. Shih-Chieh Chang, Kwang-Ting Cheng, Nam Sung Woo, Malgorzata Marek-Sadowska
    Postlayout logic restructuring using alternative wires. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:6, pp:587-596 [Journal]
  125. Chih-Wei Jim Chang, Ming-Fu Hsiao, Bo Hu, Kai Wang, Malgorzata Marek-Sadowska, Chung-Kuan Cheng, Sao-Jie Chen
    Fast postplacement optimization using functional symmetries. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:1, pp:102-118 [Journal]
  126. Chih-Wei Jim Chang, Ming-Fu Hsiao, Malgorzata Marek-Sadowska
    A new reasoning scheme for efficient redundancy addition and removal. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:7, pp:945-951 [Journal]
  127. Shih-Chieh Chang, Malgorzata Marek-Sadowska, Kwang-Ting Cheng
    Perturb and simplify: multilevel Boolean network optimizer. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:12, pp:1494-1504 [Journal]
  128. Shih-Chieh Chang, Malgorzata Marek-Sadowska, TingTing Hwang
    Technology mapping for TLU FPGAs based on decomposition of binary decision diagrams. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:10, pp:1226-1236 [Journal]
  129. Lauren Hui Chen, Malgorzata Marek-Sadowska
    Aggressor alignment for worst-case crosstalk noise. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:5, pp:612-621 [Journal]
  130. David Ihsin Cheng, Kwang-Ting Cheng, Deborah C. Wang, Malgorzata Marek-Sadowska
    A hybrid methodology for switching activities estimation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:4, pp:357-366 [Journal]
  131. Bo Hu, Malgorzata Marek-Sadowska
    Multilevel fixed-point-addition-based VLSI placement. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:8, pp:1188-1203 [Journal]
  132. Jeong-Tyng Li, Malgorzata Marek-Sadowska
    Global Routing for Gate Array. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1984, v:3, n:4, pp:298-307 [Journal]
  133. Qinghua Liu, Malgorzata Marek-Sadowska
    A study of netlist structure and placement efficiency. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:5, pp:762-772 [Journal]
  134. Qinghua Liu, Malgorzata Marek-Sadowska
    Semi-Individual Wire-Length Prediction With Application to Logic Synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:4, pp:611-624 [Journal]
  135. Chih-Chang Lin, Kuang-Chien Chen, Malgorzata Marek-Sadowska
    Logic synthesis for engineering change. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:3, pp:282-292 [Journal]
  136. Shen Lin, Ernest S. Kuh, Malgorzata Marek-Sadowska
    Stepwise equivalent conductance circuit simulation technique. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:5, pp:672-683 [Journal]
  137. Chih-Chang Lin, Malgorzata Marek-Sadowska
    On designing universal logic blocks and their application to FPGA design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:5, pp:519-527 [Journal]
  138. Chih-Chang Lin, Malgorzata Marek-Sadowska, Kwang-Ting Cheng, Mike Tien-Chien Lee
    Test-point insertion: scan paths through functional logic. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:9, pp:838-851 [Journal]
  139. Chih-Chang Lin, Malgorzata Marek-Sadowska, Mike Tien-Chien Lee, Kuang-Chien Chen
    Cost-free scan: a low-overhead scan path design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:9, pp:852-861 [Journal]
  140. Malgorzata Marek-Sadowska
    Pad Assignment for Power Nets in VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:4, pp:550-560 [Journal]
  141. Malgorzata Marek-Sadowska, Majid Sarrafzadeh
    The crossing distribution problem [IC layout]. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:4, pp:423-433 [Journal]
  142. Malgorzata Marek-Sadowska, Tom Tsan-Kuo Tarng
    Single-Layer Routing for VLSI: Analysis and Algorithms. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1983, v:2, n:4, pp:246-259 [Journal]
  143. Malgorzata Marek-Sadowska
    An Unconstrained Topological Via Minimization Problem for Two-Layer Routing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1984, v:3, n:3, pp:184-190 [Journal]
  144. Yu-Liang Wu, Malgorzata Marek-Sadowska
    Routing for array-type FPGA's. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:5, pp:506-518 [Journal]
  145. Yajun Ran, Alex Kondratyev, Kenneth H. Tseng, Yosinori Watanabe, Malgorzata Marek-Sadowska
    Eliminating false positives in crosstalk noise analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:9, pp:1406-1419 [Journal]
  146. Tom Tsan-Kuo Tarng, Malgorzata Marek-Sadowska, Ernest S. Kuh
    An Efficient Single-Row Routing Algorithm. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1984, v:3, n:3, pp:178-183 [Journal]
  147. Kun-Han Tsai, Janusz Rajski, Malgorzata Marek-Sadowska
    Star test: the theory and its applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:9, pp:1052-1064 [Journal]
  148. Ashok Vittal, Lauren Hui Chen, Malgorzata Marek-Sadowska, Kai-Ping Wang, Sherry Yang
    Crosstalk in VLSI interconnections. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:12, pp:1817-1824 [Journal]
  149. Ashok Vittal, Malgorzata Marek-Sadowska
    Crosstalk reduction for VLSI. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:3, pp:290-298 [Journal]
  150. Ashok Vittal, Malgorzata Marek-Sadowska
    Low-power buffered clock tree design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:9, pp:965-975 [Journal]
  151. Kai Wang, Malgorzata Marek-Sadowska
    On-chip power-supply network optimization using multigrid-based technique. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:3, pp:407-417 [Journal]
  152. Zhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski
    Delay-fault diagnosis using timing information. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:9, pp:1315-1325 [Journal]
  153. Zhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski
    Analysis and methodology for multiple-fault diagnosis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:3, pp:558-575 [Journal]
  154. Kai Wang, Yajun Ran, Hailin Jiang, Malgorzata Marek-Sadowska
    General skew constrained clock network sizing based on sequential linear programming. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:5, pp:773-782 [Journal]
  155. Yu-Liang Wu, Shuji Tsukiyama, Malgorzata Marek-Sadowska
    Graph based analysis of 2-D FPGA routing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:1, pp:33-44 [Journal]
  156. Amit Singh, Ganapathy Parthasarathy, Malgorzata Marek-Sadowska
    Efficient circuit clustering for area and power reduction in FPGAs. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2002, v:7, n:4, pp:643-663 [Journal]
  157. Yajun Ran, Malgorzata Marek-Sadowska
    Designing via-configurable logic blocks for regular fabric. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:1, pp:1-14 [Journal]
  158. Qinghua Liu, Bo Hu, Malgorzata Marek-Sadowska
    Individual wire-length prediction with application to timing-driven placement. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:10, pp:1004-1014 [Journal]
  159. Chao-Yang Yeh, Malgorzata Marek-Sadowska
    Sequential delay budgeting with interconnect prediction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:10, pp:1028-1037 [Journal]
  160. Yajun Ran, Malgorzata Marek-Sadowska
    Via-Configurable Routing Architectures and Fast Design Mappability Estimation for Regular Fabrics. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:9, pp:998-1009 [Journal]
  161. W. Maly, Yi-Wei Lin, Malgorzata Marek-Sadowska
    OPC-Free and Minimally Irregular IC Design Style. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:954-957 [Conf]
  162. Yu-Shih Su, Da-Chung Wang, Shih-Chieh Chang, Malgorzata Marek-Sadowska
    An Efficient Mechanism for Performance Optimization of Variable-Latency Designs. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:976-981 [Conf]
  163. Amit Singh, Arindam Mukherjee, Luca Macchiarulo, Malgorzata Marek-Sadowska
    PITIA: an FPGA for throughput-intensive applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:3, pp:354-363 [Journal]
  164. Arindam Mukherjee, Malgorzata Marek-Sadowska
    Wave steering to integrate logic and physical syntheses. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:1, pp:105-120 [Journal]
  165. Lauren Hui Chen, Malgorzata Marek-Sadowska, Forrest Brewer
    Buffer delay change in the presence of power and ground noise. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:3, pp:461-473 [Journal]

  166. Power gating scheduling for power/ground noise reduction. [Citation Graph (, )][DBLP]


  167. Engineering change using spare cells with constant insertion. [Citation Graph (, )][DBLP]


  168. Analysis and optimization of power-gated ICs with multiple power gating configurations. [Citation Graph (, )][DBLP]


  169. Power supply noise aware workload assignment for multi-core systems. [Citation Graph (, )][DBLP]


  170. Power/ground supply network optimization for power-gating. [Citation Graph (, )][DBLP]


  171. Is there always performance overhead for regular fabric? [Citation Graph (, )][DBLP]


  172. A study of reliability issues in clock distribution networks. [Citation Graph (, )][DBLP]


  173. ECO-Map: Technology remapping for post-mask ECO using simulated annealing. [Citation Graph (, )][DBLP]


  174. Timing analysis considering IR drop waveforms in power gating designs. [Citation Graph (, )][DBLP]


  175. Electromigration and voltage drop aware power grid optimization for power gated ICs. [Citation Graph (, )][DBLP]


  176. Electromigration study of power-gated grids. [Citation Graph (, )][DBLP]


  177. Transistor-level layout of high-density regular circuits. [Citation Graph (, )][DBLP]


  178. Performance study of VeSFET-based, high-density regular circuits. [Citation Graph (, )][DBLP]


  179. Timing-Aware Multiple-Delay-Fault Diagnosis. [Citation Graph (, )][DBLP]


  180. A study of decoupling capacitor effectiveness in power and ground grid networks. [Citation Graph (, )][DBLP]


  181. Statistical static timing analysis flow for transistor level macros in a microprocessor. [Citation Graph (, )][DBLP]


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