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Kuang-Chien Chen: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Chih-Chang Lin, David Ihsin Cheng, Malgorzata Marek-Sadowska, Kuang-Chien Chen
    Logic rectification and synthesis for engineering change. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1995, pp:- [Conf]
  2. Kuang-Chien Chen, Masahiro Fujita
    Efficient Sum-to-One Subsets Algorithm for Logic Optimization. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:443-448 [Conf]
  3. Kuang-Chien Chen, Saburo Muroga
    Timing Optimization for Multi-Level Combinational Networks. [Citation Graph (0, 0)][DBLP]
    DAC, 1990, pp:339-344 [Conf]
  4. Kuang-Chien Chen, Yusuke Matsunaga, Saburo Muroga, Masahiro Fujita
    A Resynthesis Approach for Network Optimization. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:458-463 [Conf]
  5. Shi-Yu Huang, Kuang-Chien Chen, Kwang-Ting Cheng
    Error Correction Based on Verification Techniques. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:258-261 [Conf]
  6. Shi-Yu Huang, Kuang-Chien Chen, Kwang-Ting Cheng, Tien-Chien Lee
    Compact Vector Generation for Accurate Power Simulation. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:161-164 [Conf]
  7. Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, Juin-Yeu Joseph Lu
    Fault-Simulation Based Design Error Diagnosis for Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:632-637 [Conf]
  8. Chih-Chang Lin, Kuang-Chien Chen, Shih-Chieh Chang, Malgorzata Marek-Sadowska, Kwang-Ting Cheng
    Logic Synthesis for Engineering Change. [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:647-652 [Conf]
  9. Feng Lu, Madhu K. Iyer, Ganapathy Parthasarathy, Li-C. Wang, Kwang-Ting Cheng, Kuang-Chien Chen
    An Efficient Sequential SAT Solver With Improved Search Strategies. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1102-1107 [Conf]
  10. Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen
    On Verifying the Correctness of Retimed Circuits. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1996, pp:277-0 [Conf]
  11. Masahiro Fujita, Yutaka Tamiya, Yuji Kukimoto, Kuang-Chien Chen
    Application of Boolean Unification to Combinational Logic Synthesis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:510-513 [Conf]
  12. Chih-Chang Lin, Mike Tien-Chien Lee, Malgorzata Marek-Sadowska, Kuang-Chien Chen
    Cost-free scan: a low-overhead scan path design methodology. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:528-533 [Conf]
  13. Kuang-Chien Chen, Masahiro Fujita
    Concurrent Resynthesis for Network Optimization. [Citation Graph (0, 0)][DBLP]
    ICCD, 1991, pp:44-48 [Conf]
  14. Jason Cong, Yuzheng Ding, Andrew B. Kahng, Peter Trajmar, Kuang-Chien Chen
    An Improved Graph-Based FPGA Techology Mapping Algorithm For Delay Optimization. [Citation Graph (0, 0)][DBLP]
    ICCD, 1992, pp:154-158 [Conf]
  15. Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, Mike Tien-Chien Lee
    A novel methodology for transistor-level power estimation. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:67-72 [Conf]
  16. Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, David Ihsin Cheng
    Error Tracer: A Fault-Simualtion-Based Approach to Design Error Diagnosis. [Citation Graph (0, 0)][DBLP]
    ITC, 1997, pp:974-981 [Conf]
  17. Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, Uwe Gläser
    An ATPG-Based Framework for Verifying Sequential Equivalence. [Citation Graph (0, 0)][DBLP]
    ITC, 1996, pp:865-874 [Conf]
  18. Chia-Chih Yen, Kuang-Chien Chen, Jing-Yang Jou
    A Practical Approach to Cycle Bound Estimation for Property Checking. [Citation Graph (0, 0)][DBLP]
    IWLS, 2002, pp:149-154 [Conf]
  19. Shi-Yu Huang, Kuang-Chien Chen, Kwang-Ting Cheng
    Incremental logic rectification. [Citation Graph (0, 0)][DBLP]
    VTS, 1997, pp:143-149 [Conf]
  20. Jason Cong, Yuzheng Ding, Tong Gao, Kuang-Chien Chen
    LUT-based FPGA technology mapping under arbitrary net-delay models. [Citation Graph (0, 0)][DBLP]
    Computers & Graphics, 1994, v:18, n:4, pp:507-516 [Journal]
  21. Kuang-Chien Chen, Jason Cong, Yuzheng Ding, Andrew B. Kahng, Peter Trajmar
    DAG-Map: Graph-Based FPGA Technology Mapping for Delay Optimization. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1992, v:9, n:3, pp:7-20 [Journal]
  22. Chia-Chih Yen, Jing-Yang Jou, Kuang-Chien Chen
    A Divide-and-Conquer-Based Algorithm for Automatic Simulation Vector Generation. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2004, v:21, n:2, pp:111-120 [Journal]
  23. Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, Chung-Yang Huang, Forrest Brewer
    AQUILA: An Equivalence Checking System for Large Sequential Designs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2000, v:49, n:5, pp:443-464 [Journal]
  24. Shi-Yu Huang, Kuang-Chien Chen, Kwang-Ting Cheng
    AutoFix: a hybrid tool for automatic logic rectification. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:9, pp:1376-1384 [Journal]
  25. Chih-Chang Lin, Kuang-Chien Chen, Malgorzata Marek-Sadowska
    Logic synthesis for engineering change. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:3, pp:282-292 [Journal]
  26. Chih-Chang Lin, Malgorzata Marek-Sadowska, Mike Tien-Chien Lee, Kuang-Chien Chen
    Cost-free scan: a low-overhead scan path design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:9, pp:852-861 [Journal]
  27. Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen
    Verifying sequential equivalence using ATPG techniques. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2001, v:6, n:2, pp:244-275 [Journal]

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