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Chi-Ming Tsai: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Rung-Bin Lin, Isaac Shuo-Hsiu Chou, Chi-Ming Tsai
    Benchmark Circuits Improve the Quality of a Standard Cell Library. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1999, pp:173-176 [Conf]
  2. Rung-Bin Lin, Chi-Ming Tsai
    Weight-Based Bus-Invert Coding for Low-Power Applications. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:121-125 [Conf]
  3. Chi-Ming Tsai, Kun-Tien Kuo, Chyi-Hui Hong, Rung-Bin Lin
    An Adaptive Interconnect-Length Driven Placer. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:393-398 [Conf]
  4. Shun-Ping Chung, Chi-Ming Tsai
    Random Early Blocking Routing in VP-Based ATM Networks. [Citation Graph (0, 0)][DBLP]
    ICOIN, 2001, pp:461-0 [Conf]
  5. Rung-Bin Lin, Chi-Ming Tsai
    Weight-Based Bus-Invert Coding for Low-Power Applications. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:121-125 [Conf]
  6. Chi-Ming Tsai, Kun-Tien Kuo, Chyi-Hui Hong, Rung-Bin Lin
    An Adaptive Interconnect-Length Driven Placer. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:393-398 [Conf]
  7. Chi-Ming Tsai, Guang-Wan Liao, Rung-Bin Lin
    A Low Power-Delay Product Page-Based Address Bus Coding Method. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:521-526 [Conf]
  8. Rung-Bin Lin, Chi-Ming Tsai
    Theoretical analysis of bus-invert coding. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:6, pp:929-934 [Journal]

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