Search the dblp DataBase
Yi-Wen Wang :
[Publications ]
[Author Rank by year ]
[Co-authors ]
[Prefers ]
[Cites ]
[Cited by ]
Publications of Author
Chang-Tzu Lin , De-Sheng Chen , Yi-Wen Wang Robust fixed-outline floorplanning through evolutionary search. [Citation Graph (0, 0)][DBLP ] ASP-DAC, 2004, pp:42-44 [Conf ] Chang-Tzu Lin , De-Sheng Chen , Yi-Wen Wang GPE: A New Representation for VLSI Floorplan Problem. [Citation Graph (0, 0)][DBLP ] ICCD, 2002, pp:42-44 [Conf ] Ching-Chung Hu , De-Sheng Chen , Yi-Wen Wang Fast multilevel floorplanning for large scale modules. [Citation Graph (0, 0)][DBLP ] ISCAS (5), 2004, pp:205-208 [Conf ] Chang-Tzu Lin , De-Sheng Chen , Yi-Wen Wang , Hsin-Hsien Ho Modem floorplanning with abutment and fixed-outline constraints. [Citation Graph (0, 0)][DBLP ] ISCAS (6), 2005, pp:6214-6217 [Conf ] Tsung-Han Tsai , Shih-Way Huang , Yi-Wen Wang Architecture design of MDCT-based psychoacoustic model co-processor in MPEG advanced audio coding. [Citation Graph (0, 0)][DBLP ] ISCAS (2), 2004, pp:761-764 [Conf ] Chang-Tzu Lin , De-Sheng Chen , Yi-Wen Wang Modern Floorplanning with Boundary and Fixed-outline Constraints via Genetic Clustering Algorithm. [Citation Graph (0, 0)][DBLP ] Journal of Circuits, Systems, and Computers, 2006, v:15, n:1, pp:107-128 [Journal ] Chang-Tzu Lin , Tai-Wei Kung , De-Sheng Chen , Yi-Wen Wang , Ching-Hwa Cheng Noise-Aware Floorplanning for Fast Power Supply Network Design. [Citation Graph (0, 0)][DBLP ] ISCAS, 2007, pp:2028-2031 [Conf ] Search in 0.001secs, Finished in 0.002secs