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Wen-Ben Jone: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Cheng-Hung Lin, Yung-Chang Huang, Shih-Chieh Chang, Wen-Ben Jone
    Design and design automation of rectification logic for engineering change. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:1006-1009 [Conf]
  2. Ching-Hwa Cheng, Wen-Ben Jone, Jinn-Shyan Wang, Shih-Chieh Chang
    Charge sharing fault analysis and testing for CMOS domino logic circuits. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2000, pp:435-440 [Conf]
  3. S. Ghosh, K. W. Lai, Wen-Ben Jone, Shih-Chieh Chang
    Scan Chain Fault Identification Using Weight-Based Codes for SoC Circuits. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2004, pp:210-215 [Conf]
  4. Der-Cheng Huang, Wen-Ben Jone
    An efficient parallel transparent diagnostic BIST. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2000, pp:299-0 [Conf]
  5. Wen-Ben Jone, Chen-Liang Fang
    Timing Optimization By Gate Resizing And Critical Path Identification. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:135-140 [Conf]
  6. Wen-Ben Jone, Christos A. Papachristou
    A Coordinated Approach to Partitioning and Test Pattern Generation for Pseudoexhaustive Testing. [Citation Graph (0, 0)][DBLP]
    DAC, 1989, pp:525-534 [Conf]
  7. Wen-Ben Jone, Christos A. Papachristou, M. Pereira
    A Scheme for Overlaying Concurrent Testing of VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1989, pp:531-536 [Conf]
  8. Ming Li, Qing-An Zeng, Wen-Ben Jone
    DyXY: a proximity congestion-aware deadlock-free dynamic routing method for network on chip. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:849-852 [Conf]
  9. Ching-Wei Yeh, Min-Cheng Chang, Shih-Chieh Chang, Wen-Ben Jone
    Gate-Level Design Exploiting Dual Supply Voltages for Power-Driven Applications. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:68-71 [Conf]
  10. Ching-Hwa Cheng, Shih-Chieh Chang, Jinn-Shyan Wang, Wen-Ben Jone
    Charge Sharing Fault Detection for CMOS Domino Logic Circuits. [Citation Graph (0, 0)][DBLP]
    DFT, 1999, pp:77-85 [Conf]
  11. Ching-Hwa Cheng, Jinn-Shyan Wang, Shih-Chieh Chang, Wen-Ben Jone
    Low-Speed Scan Testing of Charge-Sharing Faults for CMOS Domino Circuits. [Citation Graph (0, 0)][DBLP]
    DFT, 2000, pp:329-337 [Conf]
  12. J. H. Jiang, Shih-Chieh Chang, Wen-Ben Jone
    Embedded Core Testing Using Broadcast Test Architecture. [Citation Graph (0, 0)][DBLP]
    DFT, 2001, pp:95-103 [Conf]
  13. Xingguo Xiong, Yu-Liang Wu, Wen-Ben Jone
    Design and Analysis of Self-Repairable MEMS Accelerometer. [Citation Graph (0, 0)][DBLP]
    DFT, 2005, pp:21-32 [Conf]
  14. Xingguo Xiong, Yu-Liang Wu, Wen-Ben Jone
    Reliability Analysis of Self-Repairable MEMS Accelerometer. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:236-244 [Conf]
  15. Ching-Hwa Cheng, Shih-Chieh Chang, Shin-De Li, Wen-Ben Jone, Jinn-Shyan Wang
    Synthesis of CMOS Domino Circuits for Charge Sharing Alleviation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:387-390 [Conf]
  16. Anita Gleason, Wen-Ben Jone
    Reduced Hamming Count and Its Aliasing Probability. [Citation Graph (0, 0)][DBLP]
    ICCD, 1991, pp:356-359 [Conf]
  17. A. R. Nayak, Wen-Ben Jone, Sunil R. Das
    Designing General-Purpose Fault-Tolerant Distributed Systems - A Layered Approach. [Citation Graph (0, 0)][DBLP]
    ICPADS, 1994, pp:360-365 [Conf]
  18. Cheng-Juei Wu, Wen-Ben Jone
    On Multiple Fault Detection of Parity Checkers. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1515-1518 [Conf]
  19. Chingwei Yeh, Min-Cheng Chang, Shih-Chieh Chang, Wen-Ben Jone
    Power reduction through iterative gate sizing and voltage scaling. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 1999, pp:246-249 [Conf]
  20. Rui Min, Wen-Ben Jone, Yiming Hu
    Phased tag cache: an efficient low power cache system. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:805-808 [Conf]
  21. Rui Min, Wen-Ben Jone, Yiming Hu
    Location cache: a low-power L2 cache system. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:120-125 [Conf]
  22. Ming Li, Wen-Ben Jone, Qing-An Zeng
    An Efficient Wrapper Scan Chain Configuration Method for Network-on-Chip Testing. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:147-152 [Conf]
  23. Shih-Chieh Chang, Shi-Sen Chang, Wen-Ben Jone, Chien-Chung Tsai
    A novel combinational testability analysis by considering signal correlation. [Citation Graph (0, 0)][DBLP]
    ITC, 1998, pp:658-667 [Conf]
  24. Paresh Gondalia, Allan Gutjahr, Wen-Ben Jone
    Realizing a High Measure of Confidence for Defect Level Analysis of Random Testing. [Citation Graph (0, 0)][DBLP]
    ITC, 1993, pp:478-487 [Conf]
  25. Wen-Ben Jone
    Defect Level Estimation of Random and Pseudorandom Testing. [Citation Graph (0, 0)][DBLP]
    ITC, 1991, pp:712-721 [Conf]
  26. Wen-Ben Jone, Jiann-Chyi Rau, Shih-Chieh Chang, Yu-Liang Wu
    A tree-structured LFSR synthesis scheme for pseudo-exhaustive testing of VLSI circuits. [Citation Graph (0, 0)][DBLP]
    ITC, 1998, pp:322-330 [Conf]
  27. Sunil R. Das, N. Goel, Wen-Ben Jone, A. R. Nayak
    Syndrome signature in output compaction for VLSI BIST. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1996, pp:337-338 [Conf]
  28. Sunil R. Das, H. T. Ho, Wen-Ben Jone, A. R. Nayak
    An improved output compaction technique for built-in self-test in VLSI circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:403-407 [Conf]
  29. Sunil R. Das, Wen-Ben Jone, Amiya Nayak, Ian Choi
    On Probabilistic Testing of Large-Scale Sequential Circuits Using Circuit Decomposition. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:311-314 [Conf]
  30. Der-Cheng Huang, Wen-Ben Jone, Sunil R. Das
    An Efficient Parallel Transparent Bist Method For Multiple Embedded Memory Buffers. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:379-384 [Conf]
  31. Der-Cheng Huang, Wen-Ben Jone, Sunil R. Das
    A Parallel Built-In Self-Diagnostic Method For Embedded Memory Buffers. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:397-402 [Conf]
  32. Wen-Ben Jone, Sunil R. Das
    CACOP - A Random Pattern Testability Analyzer. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:61-64 [Conf]
  33. Wen-Ben Jone, Sunil R. Das
    A Stochastic Method for Defect Level Analysis of Pseudorandom Testing. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1998, pp:382-0 [Conf]
  34. Wen-Ben Jone, Yun-Pan Ho, Sunil R. Das
    Delay Fault Coverage Enhancement Using Multiple Test Observation Times. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:106-110 [Conf]
  35. Rui Min, Zhiyong Xu, Yiming Hu, Wen-Ben Jone
    Partial Tag Comparison: A New Technology for Power-Efficient Set-Associative Cache Designs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:183-188 [Conf]
  36. Wen-Ben Jone, Der-Cheng Huang, S. C. Wu, K. J. Lee
    An Efficient BIST Method for Small Buffers. [Citation Graph (0, 0)][DBLP]
    VTS, 1999, pp:246-251 [Conf]
  37. Xingguo Xiong, Yu-Liang Wu, Wen-Ben Jone
    A Dual-Mode Built-In Self-Test Technique for Capacitive MEMS Devices. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:148-153 [Conf]
  38. Wen-Ben Jone, Cheng-Juei Wu
    Multiple Fault Detection in Parity Checkers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1994, v:43, n:9, pp:1096-1099 [Journal]
  39. Shih-Chieh Chang, Ching-Hwa Cheng, Wen-Ben Jone, Shin-De Lee, Jinn-Shyan Wang
    Charge-sharing alleviation and detection for CMOS domino circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:2, pp:266-280 [Journal]
  40. Shih-Chieh Chang, Wen-Ben Jone, Shi-Sen Chang
    TAIR: testability analysis by implication reasoning. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:1, pp:152-160 [Journal]
  41. Chen-Liang Fang, Wen-Ben Jone
    Timing optimization by gate resizing and critical path identification. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:2, pp:201-217 [Journal]
  42. Der-Cheng Huang, Wen-Ben Jone
    A parallel built-in self-diagnostic method for embedded memoryarrays. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:4, pp:449-465 [Journal]
  43. Der-Cheng Huang, Wen-Ben Jone
    A parallel transparent BIST method for embedded memory arrays bytolerating redundant operations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:5, pp:617-628 [Journal]
  44. Wen-Ben Jone
    Defect level estimation of circuit testing using sequential statistical analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:2, pp:336-348 [Journal]
  45. Wen-Ben Jone, Patrick H. Madden
    Multiple fault testing using minimal single fault test set for fanout-free circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:1, pp:149-157 [Journal]
  46. Wen-Ben Jone, Christos A. Papachristou
    A coordinated circuit partitioning and test generation method for pseudo-exhaustive testing of VLSI circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:3, pp:374-384 [Journal]
  47. Dan Li, Wen-Ben Jone
    Pseudorandom test-length analysis using differential solutions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:7, pp:815-825 [Journal]
  48. Wen-Ben Jone, K. S. Tsai
    Confidence analysis for defect-level estimation of VLSI random testing. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1998, v:3, n:3, pp:389-407 [Journal]
  49. Wen-Ben Jone, Jinn-Shyan Wang, Hsueh-I Lu, I. P. Hsu, J.-Y. Chen
    Design theory and implementation for low-power segmented bus systems. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2003, v:8, n:1, pp:38-54 [Journal]
  50. Wen-Ben Jone, Paresh Gondalia, Allan Gutjahr
    Realizing a high measure of confidence for defect level analysis of random testing [VLSI]. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1995, v:3, n:3, pp:446-450 [Journal]
  51. J.-Y. Chen, Wen-Ben Jone, Jinn-Shyan Wang, Hsueh-I Lu, T. F. Chen
    Segmented bus design for low-power systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1999, v:7, n:1, pp:25-29 [Journal]
  52. Wen-Ben Jone, Der-Cheng Huang, S. C. Wu, K. J. Lee
    An efficient BIST method for distributed small buffers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:4, pp:512-515 [Journal]

  53. Analysis of Resistive Bridging Defects in a Synchronizer. [Citation Graph (, )][DBLP]


  54. Selective light Vth hopping (SLITH): Bridging the gap between runtime dynamic and leakage. [Citation Graph (, )][DBLP]


  55. Material Fatigue and Reliability of MEMS Accelerometers. [Citation Graph (, )][DBLP]


  56. Analysis of Resistive Open Defects in a Synchronizer. [Citation Graph (, )][DBLP]


  57. Accurate energy breakeven time estimation for run-time power gating. [Citation Graph (, )][DBLP]


  58. Temporal and spatial idleness exploitation for optimal-grained leakage control. [Citation Graph (, )][DBLP]


  59. An efficient routing method for pseudo-exhaustive built-in self-testing of high-speed interconnects. [Citation Graph (, )][DBLP]


  60. Run-time Active Leakage Reduction by power gating and reverse body biasing: An eNERGY vIEW. [Citation Graph (, )][DBLP]


  61. Dynamic virtual ground voltage estimation for power gating. [Citation Graph (, )][DBLP]


  62. Novel Vth Hopping Techniques for Aggressive Runtime Leakage Control. [Citation Graph (, )][DBLP]


  63. Control Circuitry for Self-Repairable MEMS Accelerometers. [Citation Graph (, )][DBLP]


  64. Turbo1500: Core-Based Design for Test and Diagnosis. [Citation Graph (, )][DBLP]


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