Search the dblp DataBase

Publications of Author

1. Yung-Chia Lin, Chung-Wen Huang, Jenq Kuen Lee
   System-level design space exploration for security processor prototyping in analytical approaches. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2005, pp:376-380 [Conf]
   
2. Yung-Chia Lin, Yuan-Shin Hwang, Jenq Kuen Lee
   Compiler Optimizations with DSP-Specific Semantic Descriptions. [Citation Graph (0, 0)][DBLP]
   LCPC, 2002, pp:75-89 [Conf]
   
3. Yung-Chia Lin, Yi-Ping You, Chung-Wen Huang, Jenq Kuen Lee, Wei-Kuan Shih, TingTing Hwang
   Power-Aware Scheduling for Parallel Security Processors with Analytical Models. [Citation Graph (0, 0)][DBLP]
   LCPC, 2004, pp:470-484 [Conf]
   
4. Yung-Chia Lin, Chung-Lin Tang, Chung-Ju Wu, Ming-Yu Hung, Yi-Ping You, Ya-Chiao Moo, Sheng-Yuan Chen, Jenq Kuen Lee
   Compiler Supports and Optimizations for PAC VLIW DSP Processors. [Citation Graph (0, 0)][DBLP]
   LCPC, 2005, pp:466-474 [Conf]
   
5. Chi Wu, Kun-Yuan Hsieh, Yung-Chia Lin, Chung-Ju Wu, Wen-Li Shih, Shih-Chang Chen, Chung-Kai Chen, Chien-Ching Huang, Yi-Ping You, Jenq Kuen Lee
   Integrating Compiler and System Toolkit Flow for Embedded VLIW DSP Processors. [Citation Graph (0, 0)][DBLP]
   RTCSA, 2006, pp:215-222 [Conf]
   
6. 
   An MILP-based wire spreading algorithm for PSM-aware layout modification. [Citation Graph (, )][DBLP]
   
   
7. 
   PALF: compiler supports for irregular register files in clustered VLIW DSP processors. [Citation Graph (, )][DBLP]
   
   
8. 
   LC-GRFA: global register file assignment with local consciousness for VLIW DSP processors with non-uniform register files. [Citation Graph (, )][DBLP]