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Iris Hui-Ru Jiang: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Jiann-Horng Lin, Jing-Yang Jou, Iris Hui-Ru Jiang
    Hierarchical Floorplan Design on the Internet. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1999, pp:189-192 [Conf]
  2. Iris Hui-Ru Jiang, Jing-Yang Jou, Yao-Wen Chang
    Noise-Constrained Performance Optimization by Simultaneous Gate and Wire Sizing Based on Lagrangian Relaxation. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:90-95 [Conf]
  3. Mango Chia-Tso Chao, Guang-Ming Wu, Iris Hui-Ru Jiang, Yao-Wen Chang
    A clustering- and probability-based approach for time-multiplexed FPGA partitioning. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:364-369 [Conf]
  4. Jie-Hong Roland Jiang, Iris Hui-Ru Jiang
    Optimum loading dispersion for high-speed tree-type decision circuitry. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:520-525 [Conf]
  5. Iris Hui-Ru Jiang, Song-Ra Pan, Yao-Wen Chang, Jing-Yang Jou
    Optimal reliable crosstalk-driven interconnect optimization. [Citation Graph (0, 0)][DBLP]
    ISPD, 2000, pp:128-133 [Conf]
  6. Nicholas Chia-Yuan Chang, Yao-Wen Chang, Iris Hui-Ru Jiang
    Formulae for Performance Optimization and Their Applications to Interconnect-Driven Floorplanning. [Citation Graph (0, 0)][DBLP]
    ISQED, 2002, pp:523-528 [Conf]
  7. Iris Hui-Ru Jiang, Yao-Wen Chang, Jing-Yang Jou
    Crosstalk-driven interconnect optimization by simultaneous gate andwire sizing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:9, pp:999-1010 [Journal]
  8. Iris Hui-Ru Jiang, Yao-Wen Chang, Jing-Yang Jou, Kai-Yuan Chao
    Simultaneous floor plan and buffer-block optimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:5, pp:694-703 [Journal]
  9. Iris Hui-Ru Jiang, Song-Ra Pan, Yao-Wen Chang, Jing-Yang Jou
    Reliable crosstalk-driven interconnect optimization. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2006, v:11, n:1, pp:88-103 [Journal]

  10. Matching-based minimum-cost spare cell selection for design changes. [Citation Graph (, )][DBLP]


  11. VIFI-CMP: variability-tolerant chip-multiprocessors for throughput and power. [Citation Graph (, )][DBLP]


  12. Configurable rectilinear Steiner tree construction for SoC and nano technologies. [Citation Graph (, )][DBLP]


  13. Power-state-aware buffered tree construction. [Citation Graph (, )][DBLP]


  14. Optimal wiring topology for electromigration avoidance considering multiple layers and obstacles. [Citation Graph (, )][DBLP]


  15. Analog placement and global routing considering wiring symmetry. [Citation Graph (, )][DBLP]


  16. Unification of obstacle-avoiding rectilinear Steiner tree construction. [Citation Graph (, )][DBLP]


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