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Xijiang Lin: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Xijiang Lin, Janusz Rajski
    Propagation delay fault: a new fault model to test delay faults. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:178-183 [Conf]
  2. Irith Pomeranz, Sudhakar M. Reddy, Xijiang Lin
    Experimental Results of Forward-Looking Reverse Order Fault Simulation on Industrial Circuits with Scan. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2001, pp:467- [Conf]
  3. Xijiang Lin, Rob Thompson
    Test generation for designs with multiple clocks. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:662-667 [Conf]
  4. Matthias Beck, Olivier Barondeau, Martin Kaibel, Frank Poehl, Xijiang Lin, Ron Press
    Logic Design for On-Chip Test Clock Generation - Implementation Details and Impact on Delay Test Quality. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:56-61 [Conf]
  5. Xijiang Lin, Irith Pomeranz, Sudhakar M. Reddy
    Full Scan Fault Coverage With Partial Scan. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:468-472 [Conf]
  6. Xijiang Lin, Irith Pomeranz, Sudhakar M. Reddy
    Techniques for improving the efficiency of sequential circuit test generation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:147-151 [Conf]
  7. Chen Wang, Sudhakar M. Reddy, Irith Pomeranz, Xijiang Lin, Janusz Rajski
    Conflict driven techniques for improving deterministic test pattern generation. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:87-93 [Conf]
  8. Xijiang Lin, Janusz Rajski, Irith Pomeranz, Sudhakar M. Reddy
    On static test compaction and test pattern ordering for scan designs. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:1088-1097 [Conf]
  9. Xijiang Lin, Irith Pomeranz, Sudhakar M. Reddy
    MIX: A Test Generation System for Synchronous Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1998, pp:456-463 [Conf]
  10. Santiago Remersaro, Xijiang Lin, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski
    Low Shift and Capture Power Scan Tests. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:793-798 [Conf]
  11. Matthias Beck, Olivier Barondeau, Frank Poehl, Xijiang Lin, Ron Press
    Measures to Improve Delay Fault Testing on Low-Cost Testers - A Case Study. [Citation Graph (0, 0)][DBLP]
    VTS, 2005, pp:223-228 [Conf]
  12. Xijiang Lin, Wu-Tung Cheng, Irith Pomeranz, Sudhakar M. Reddy
    SIFAR: Static Test Compaction for Synchronous Sequential Circuits Based on Single Fault Restoration. [Citation Graph (0, 0)][DBLP]
    VTS, 2000, pp:205-212 [Conf]
  13. Xijiang Lin, Irith Pomeranz, Sudhakar M. Reddy
    On Removing Redundant Faults in Synchronous Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:168-175 [Conf]
  14. Xijiang Lin, Janusz Rajski
    The Impacts of Untestable Defects on Transition Fault Testing. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:2-7 [Conf]
  15. Sudhakar M. Reddy, Irith Pomeranz, Nadir Z. Basturkmen, Xijiang Lin
    Procedures for Identifying Undetectable and Redundant Faults In Synchronous Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    VTS, 1999, pp:275-283 [Conf]
  16. Nandu Tendolkar, Rajesh Raina, Rick Woltenberg, Xijiang Lin, Bruce Swanson, Greg Aldrich
    Novel Techniques for Achieving High At-Speed Transition Fault Test Coverage for Motorola's Microprocessors Based on PowerPC(tm) Instruction Set Architecture. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:3-8 [Conf]
  17. Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz, Xijiang Lin, Janusz Rajski
    Scan Tests with Multiple Fault Activation Cycles for Delay Faults. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:343-348 [Conf]
  18. Xijiang Lin, Ron Press, Janusz Rajski, Paul Reuter, Thomas Rinderknecht, Bruce Swanson, Nagesh Tamarapalli
    High-Frequency, At-Speed Scan Testing. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2003, v:20, n:5, pp:17-25 [Journal]
  19. Matthias Beck, Olivier Barondeau, Martin Kaibel, Frank Poehl, Xijiang Lin, Ron Press
    Logic Design for On-Chip Test Clock Generation - Implementation Details and Impact on Delay Test Quality [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]

  20. Test Generation for Designs with On-Chip Clock Generators. [Citation Graph (, )][DBLP]


  21. Reducing Scan Shift Power at RTL. [Citation Graph (, )][DBLP]


  22. Scan-Based Tests with Low Switching Activity. [Citation Graph (, )][DBLP]


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