The SCEAS System
| |||||||

## Search the dblp DataBase
Jai-Ming Lin:
[Publications]
[Author Rank by year]
[Co-authors]
[Prefers]
[Cites]
[Cited by]
## Publications of Author- Jai-Ming Lin, Guang-Ming Wu, Yao-Wen Chang, Jen-Hui Chuang
**Placement with symmetry constraints for analog layout design using TCG-S.**[Citation Graph (0, 0)][DBLP] ASP-DAC, 2005, pp:1135-1137 [Conf] - Jai-Ming Lin, Yao-Wen Chang
**TCG: A Transitive Closure Graph-Based Representation for Non-Slicing Floorplans.**[Citation Graph (0, 0)][DBLP] DAC, 2001, pp:764-769 [Conf] - Jai-Ming Lin, Yao-Wen Chang
**TCG-S: orthogonal coupling of P**[Citation Graph (0, 0)][DBLP]^{*}-admissible representations for general floorplans. DAC, 2002, pp:842-847 [Conf] - Jai-Ming Lin, Hsin-Lung Chen, Yao-Wen Chang
**Arbitrary Convex and Concave Rectilinear Module Packing Using TCG.**[Citation Graph (0, 0)][DBLP] DATE, 2002, pp:69-77 [Conf] - Yao-Wen Chang, Jai-Ming Lin, D. F. Wong
**Graph matching-based algorithms for FPGA segmentation design.**[Citation Graph (0, 0)][DBLP] ICCAD, 1998, pp:34-39 [Conf] - Guang-Ming Wu, Jai-Ming Lin, Yao-Wen Chang
**An Algorithm for Dynamically Reconfigurable FPGA Placement.**[Citation Graph (0, 0)][DBLP] ICCD, 2001, pp:501-504 [Conf] - Guang-Ming Wu, Jai-Ming Lin, Mango Chia-Tso Chao, Yao-Wen Chang
**Generic ILP-Based Approaches for Dynamically Reconfigurable FPGA Partitioning.**[Citation Graph (0, 0)][DBLP] ICCD, 2001, pp:335-347 [Conf] - Yao-Wen Chang, Jai-Ming Lin, Martin D. F. Wong
**Matching-based algorithm for FPGA channel segmentation design.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:6, pp:784-791 [Journal] - Jai-Ming Lin, Yao-Wen Chang
**TCG-S: orthogonal coupling of P/sup */-admissible representations for general floorplans.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:6, pp:968-980 [Journal] - Guang-Ming Wu, Jai-Ming Lin, Yao-Wen Chang
**Generic ILP-based approaches for time-multiplexed FPGA partitioning.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:10, pp:1266-1274 [Journal] - Guang-Ming Wu, Jai-Ming Lin, Yao-Wen Chang
**Performance-driven placement for dynamically reconfigurable FPGAs.**[Citation Graph (0, 0)][DBLP] ACM Trans. Design Autom. Electr. Syst., 2002, v:7, n:4, pp:628-642 [Journal] - Jai-Ming Lin, Yao-Wen Chang
**TCG: A transitive closure graph-based representation for general floorplans.**[Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2005, v:13, n:2, pp:288-292 [Journal] - Jai-Ming Lin, Hsin-Lung Chen, Yao-Wen Chang
**Arbitrarily shaped rectilinear module placement using the transitive closure graph representation.**[Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2002, v:10, n:6, pp:886-901 [Journal] - Jai-Ming Lin, Yao-Wen Chang, Shih-Ping Lin
**Corner sequence - a P-admissible floorplan representation with a worst case linear-time packing scheme.**[Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2003, v:11, n:4, pp:679-686 [Journal] **Performance-driven analog placement considering boundary constraint.**[Citation Graph (, )][DBLP]
Search in 0.002secs, Finished in 0.003secs | |||||||

| |||||||

| |||||||

System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002 for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002 |