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Chia-Chih Yen:
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- Hue-Min Lin, Chia-Chih Yen, Che-Hua Shih, Jing-Yang Jou
On compliance test of on-chip bus for SOC. [Citation Graph (0, 0)][DBLP] ASP-DAC, 2004, pp:328-333 [Conf]
- Chien-Nan Jimmy Liu, Chia-Chih Yen, Jing-Yang Jou
Automatic Functional Vector Generation Using the Interacting FSM Model. [Citation Graph (0, 0)][DBLP] ISQED, 2001, pp:372-377 [Conf]
- Chia-Chih Yen, Kuang-Chien Chen, Jing-Yang Jou
A Practical Approach to Cycle Bound Estimation for Property Checking. [Citation Graph (0, 0)][DBLP] IWLS, 2002, pp:149-154 [Conf]
- Chia-Chih Yen, Ten Lin, Hermes Lin, Kai Yang, Tayung Liu, Yu-Chin Hsu
Diagnosing Silicon Failures Based on Functional Test Patterns. [Citation Graph (0, 0)][DBLP] MTV, 2006, pp:94-98 [Conf]
- Chia-Chih Yen, Jing-Yang Jou, Kuang-Chien Chen
A Divide-and-Conquer-Based Algorithm for Automatic Simulation Vector Generation. [Citation Graph (0, 0)][DBLP] IEEE Design & Test of Computers, 2004, v:21, n:2, pp:111-120 [Journal]
- Chia-Chih Yen, Jing-Yang Jou
An Optimum Algorithm for Compacting Error Traces for Efficient Design Error Debugging. [Citation Graph (0, 0)][DBLP] IEEE Trans. Computers, 2006, v:55, n:11, pp:1356-1366 [Journal]
A General Failure Candidate Ranking Framework for Silicon Debug. [Citation Graph (, )][DBLP]
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