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Jing-Jia Liou: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Jing-Jia Liou, Angela Krstic, Kwang-Ting Cheng, Deb Aditya Mukherjee, Sandip Kundu
    Performance sensitivity analysis using statistical method and its applications to delay. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:587-592 [Conf]
  2. Angela Krstic, Li-C. Wang, Kwang-Ting Cheng, Jing-Jia Liou, T. M. Mak
    Enhancing diagnosis resolution for delay defects based upon statistical timing and statistical fault models. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:668-673 [Conf]
  3. Jing-Jia Liou, Kwang-Ting Cheng, Sandip Kundu, Angela Krstic
    Fast Statistical Timing Analysis By Probabilistic Event Propagation. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:661-666 [Conf]
  4. Jing-Jia Liou, Angela Krstic, Li-C. Wang, Kwang-Ting Cheng
    False-path-aware statistical timing analysis and efficient path selection for delay testing and timing validation. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:566-569 [Conf]
  5. Jing-Jia Liou, Li-C. Wang, Kwang-Ting Cheng, Jennifer Dworak, M. Ray Mercer, Rohit Kapur, Thomas W. Williams
    Enhancing test efficiency for delay fault testing using multiple-clocked schemes. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:371-374 [Conf]
  6. Angela Krstic, Li-C. Wang, Kwang-Ting Cheng, Jing-Jia Liou, Magdy S. Abadir
    Delay Defect Diagnosis Based Upon Statistical Timing Models - The First Step. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10328-10335 [Conf]
  7. Yen-Lin Peng, Jing-Jia Liou, Chih-Tsun Huang, Cheng-Wen Wu
    An Application-Independent Delay Testing Methodology for Island-Style FPGA. [Citation Graph (0, 0)][DBLP]
    DFT, 2004, pp:478-486 [Conf]
  8. Ying-Yen Chen, Jing-Jia Liou
    Enhancing Diagnosis Resolution For Delay Faults By Path Extension Method. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:428-438 [Conf]
  9. Jing-Jia Liou, Angela Krstic, Yi-Min Jiang, Kwang-Ting Cheng
    Path Selection and Pattern Generation for Dynamic Timing Analysis Considering Power Supply Noise Effects. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:493-496 [Conf]
  10. Jing-Jia Liou, Li-C. Wang, Kwang-Ting Cheng
    On theoretical and practical considerations of path selection for delay fault testing. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:94-100 [Conf]
  11. Shun-Yen Lu, Pei-Ying Hsieh, Jing-Jia Liou
    Exploring linear structures of critical path delay faults to reduce test efforts. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:100-106 [Conf]
  12. Angela Krstic, Jing-Jia Liou, Kwang-Ting Cheng, Li-C. Wang
    On Structural vs. Functional Testing for Delay Faults. [Citation Graph (0, 0)][DBLP]
    ISQED, 2003, pp:438-441 [Conf]
  13. Angela Krstic, Jing-Jia Liou, Yi-Min Jiang, Kwang-Ting Cheng
    Delay testing considering crosstalk-induced effects. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:558-567 [Conf]
  14. Jing-Jia Liou, Li-C. Wang, Kwang-Ting Cheng, Jennifer Dworak, M. Ray Mercer, Rohit Kapur, Thomas W. Williams
    Analysis of Delay Test Effectiveness with a Multiple-Clock Scheme. [Citation Graph (0, 0)][DBLP]
    ITC, 2002, pp:407-416 [Conf]
  15. Angela Krstic, Li-C. Wang, Kwang-Ting Cheng, Jing-Jia Liou
    Diagnosis of Delay Defects Using Statistical Timing Models. [Citation Graph (0, 0)][DBLP]
    VTS, 2003, pp:339-344 [Conf]
  16. Jing-Jia Liou, Kwang-Ting Cheng, Deb Aditya Mukherjee
    Path Selection for Delay Testing of Deep Sub-Micron Devices Using Statistical Performance Sensitivity Analysis. [Citation Graph (0, 0)][DBLP]
    VTS, 2000, pp:97-104 [Conf]
  17. Chun-Chieh Wang, Jing-Jia Liou, Yen-Lin Peng, Chih-Tsun Huang, Cheng-Wen Wu
    A BIST Scheme for FPGA Interconnect Delay Faults. [Citation Graph (0, 0)][DBLP]
    VTS, 2005, pp:201-206 [Conf]
  18. Jyun-Wei Chen, Ying-Yen Chen, Jing-Jia Liou
    Handling Pattern-Dependent Delay Faults in Diagnosis. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:151-157 [Conf]
  19. Jing-Jia Liou, Angela Krstic, Yi-Min Jiang, Kwang-Ting Cheng
    Modeling, testing, and analysis for delay defects and noise effects in deep submicron devices. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:6, pp:756-769 [Journal]
  20. Li-C. Wang, Jing-Jia Liou, Kwang-Ting Cheng
    Critical path selection for delay fault testing based upon a statistical timing model. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:11, pp:1550-1565 [Journal]
  21. Ying-Yen Chen, Jing-Jia Liou
    Extraction of Statistical Timing Profiles Using Test Data. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:509-514 [Conf]

  22. A Non-Intrusive and Accurate Inspection Method for Segment Delay Variabilities. [Citation Graph (, )][DBLP]


  23. Multiple-Core under Test Architecture for HOY Wireless Testing Platform. [Citation Graph (, )][DBLP]


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