The SCEAS System
Navigation Menu
Introduction
Collection Based
Clustering
Ranking
Paper Based
Journals
Conferences
DB Status
Statistics
Search

Search the dblp DataBase

Title:
Author:
Angela Krstic: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Jing-Jia Liou, Angela Krstic, Kwang-Ting Cheng, Deb Aditya Mukherjee, Sandip Kundu
    Performance sensitivity analysis using statistical method and its applications to delay. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:587-592 [Conf]
  2. Yi-Min Jiang, Angela Krstic, Kwang-Ting Cheng, Malgorzata Marek-Sadowska
    Post-Layout Logic Restructuring for Performance Optimization. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:662-665 [Conf]
  3. Angela Krstic, Kwang-Ting Cheng
    Vector Generation for Maximum Instantaneous Current Through Supply Lines for CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:383-388 [Conf]
  4. Angela Krstic, Wei-Cheng Lai, Kwang-Ting Cheng, Li Chen, Sujit Dey
    Embedded software-based self-testing for SoC design. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:355-360 [Conf]
  5. Angela Krstic, Li-C. Wang, Kwang-Ting Cheng, Jing-Jia Liou, T. M. Mak
    Enhancing diagnosis resolution for delay defects based upon statistical timing and statistical fault models. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:668-673 [Conf]
  6. Jing-Jia Liou, Kwang-Ting Cheng, Sandip Kundu, Angela Krstic
    Fast Statistical Timing Analysis By Probabilistic Event Propagation. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:661-666 [Conf]
  7. Jing-Jia Liou, Angela Krstic, Li-C. Wang, Kwang-Ting Cheng
    False-path-aware statistical timing analysis and efficient path selection for delay testing and timing validation. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:566-569 [Conf]
  8. Angela Krstic, Li-C. Wang, Kwang-Ting Cheng, Jing-Jia Liou, Magdy S. Abadir
    Delay Defect Diagnosis Based Upon Statistical Timing Models - The First Step. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10328-10335 [Conf]
  9. Jing-Jia Liou, Angela Krstic, Yi-Min Jiang, Kwang-Ting Cheng
    Path Selection and Pattern Generation for Dynamic Timing Analysis Considering Power Supply Noise Effects. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:493-496 [Conf]
  10. Yi-Min Jiang, Angela Krstic, Kwang-Ting Cheng
    Dynamic Timing Analysis Considering Power Supply Noise Effects. [Citation Graph (0, 0)][DBLP]
    ISQED, 2000, pp:137-144 [Conf]
  11. Angela Krstic, Jing-Jia Liou, Kwang-Ting Cheng, Li-C. Wang
    On Structural vs. Functional Testing for Delay Faults. [Citation Graph (0, 0)][DBLP]
    ISQED, 2003, pp:438-441 [Conf]
  12. Xiaoliang Bai, Sujit Dey, Angela Krstic
    HyAC: A Hybrid Structural SAT Based ATPG for Crosstalk. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:112-121 [Conf]
  13. Yi-Min Jiang, Angela Krstic, Kwang-Ting Cheng
    Delay testing considering power supply noise effects. [Citation Graph (0, 0)][DBLP]
    ITC, 1999, pp:181-190 [Conf]
  14. Angela Krstic, Kwang-Ting Cheng, Srimat T. Chakradhar
    Identification and Test Generation for Primitive Faults. [Citation Graph (0, 0)][DBLP]
    ITC, 1996, pp:423-432 [Conf]
  15. Angela Krstic, Kwang-Ting Cheng, Srimat T. Chakradhar
    Design for Primitive Delay Fault Testability. [Citation Graph (0, 0)][DBLP]
    ITC, 1997, pp:436-445 [Conf]
  16. Angela Krstic, Jing-Jia Liou, Yi-Min Jiang, Kwang-Ting Cheng
    Delay testing considering crosstalk-induced effects. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:558-567 [Conf]
  17. Angela Krstic, Li-C. Wang, Kwang-Ting Cheng, T. M. Mak
    Diagnosis-Based Post-Silicon Timing Validation Using Statistical Tools and Methodologies. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:339-348 [Conf]
  18. Wei-Cheng Lai, Angela Krstic, Kwang-Ting Cheng
    Test program synthesis for path delay faults in microprocessor cores. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:1080-1089 [Conf]
  19. Li-C. Wang, Angela Krstic, Leonard Lee, Kwang-Ting Cheng, M. Ray Mercer, Thomas W. Williams, Magdy S. Abadir
    Using Logic Models To Predict The Detection Behavior Of Statistical Timing Defects. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:1041-1050 [Conf]
  20. Angela Krstic, Kwang-Ting Cheng
    Generation of high quality tests for functional sensitizable paths. [Citation Graph (0, 0)][DBLP]
    VTS, 1995, pp:374-379 [Conf]
  21. Angela Krstic, Kwang-Ting (Tim) Cheng, Srimat T. Chakradhar
    Testing High Speed VLSI Devices Using Slower Testers. [Citation Graph (0, 0)][DBLP]
    VTS, 1999, pp:16-21 [Conf]
  22. Angela Krstic, Li-C. Wang, Kwang-Ting Cheng, Jing-Jia Liou
    Diagnosis of Delay Defects Using Statistical Timing Models. [Citation Graph (0, 0)][DBLP]
    VTS, 2003, pp:339-344 [Conf]
  23. Wei-Cheng Lai, Angela Krstic, Kwang-Ting Cheng
    On Testing the Path Delay Faults of a Microprocessor Using its Instruction Set. [Citation Graph (0, 0)][DBLP]
    VTS, 2000, pp:15-22 [Conf]
  24. Kwang-Ting Cheng, Angela Krstic
    Current Directions in Automatic Test-Pattern Generation. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1999, v:32, n:11, pp:58-64 [Journal]
  25. Angela Krstic, Wei-Cheng Lai, Kwang-Ting Cheng, Li Chen, Sujit Dey
    Embedded Software-Based Self-Test for Programmable Core-Based Designs. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2002, v:19, n:4, pp:18-27 [Journal]
  26. Wei-Cheng Lai, Angela Krstic, Kwang-Ting (Tim) Cheng
    Functionally Testable Path Delay Faults on a Microprocessor. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2000, v:17, n:4, pp:6-14 [Journal]
  27. T. M. Mak, Angela Krstic, Kwang-Ting (Tim) Cheng, Li-C. Wang
    New Challenges in Delay Testing of Nanometer, Multigigahertz Designs. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2004, v:21, n:3, pp:241-247 [Journal]
  28. Angela Krstic, Srimat T. Chakradhar, Kwang-Ting Cheng
    Testable Path Delay Fault Cover for Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    J. Inf. Sci. Eng., 2000, v:16, n:5, pp:673-686 [Journal]
  29. Kwang-Ting Cheng, Angela Krstic, Hsi-Chuan Chen
    Generation of High Quality Tests for Robustly Untestable Path Delay Faults. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1996, v:45, n:12, pp:1379-1392 [Journal]
  30. Angela Krstic, Kwang-Ting Cheng, Srimat T. Chakradhar
    Primitive delay faults: identification, testing, and design for testability. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:6, pp:669-684 [Journal]
  31. Angela Krstic, Yi-Min Jiang, Kwang-Ting Cheng
    Pattern generation for delay testing and dynamic timing analysisconsidering power-supply noise effects. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:3, pp:416-425 [Journal]
  32. Jing-Jia Liou, Angela Krstic, Yi-Min Jiang, Kwang-Ting Cheng
    Modeling, testing, and analysis for delay defects and noise effects in deep submicron devices. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:6, pp:756-769 [Journal]
  33. Yi-Min Jiang, Angela Krstic, Kwang-Ting Cheng
    Estimation for maximum instantaneous current through supply lines for CMOS circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:1, pp:61-73 [Journal]

Search in 0.002secs, Finished in 0.303secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
Introduction Collection Based Clustering Ranking Paper Based Journals Conferences DB Status Statistics Search
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002