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I-Min Liu: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. I-Min Liu, Hung-Ming Chen, Tan-Li Chou, Adnan Aziz, D. F. Wong
    Integrated power supply planning and floorplanning. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:589-594 [Conf]
  2. Huaizhi Wu, Martin D. F. Wong, I-Min Liu
    Timing-constrained and voltage-island-aware voltage assignment. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:429-432 [Conf]
  3. Hai Zhou, D. F. Wong, I-Min Liu, Adnan Aziz
    Simultaneous Routing and Buffer Insertion with Restrictions on Buffer Locations. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:96-99 [Conf]
  4. Li-Da Huang, Xiaoping Tang, Hua Xiang, D. F. Wong, I-Min Liu
    A Polynomial Time Optimal Diode Insertion/Routing Algorithm for Fixing Antenna Problem. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:470-477 [Conf]
  5. I-Min Liu, Adnan Aziz, D. F. Wong
    Meeting Delay Constraints in DSM by Minimal Repeater Insertion. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:436-440 [Conf]
  6. Huaizhi Wu, I-Min Liu, Martin D. F. Wong, Yusu Wang
    Post-placement voltage island generation under performance requirement. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:309-316 [Conf]
  7. Hung-Ming Chen, I-Min Liu, Martin D. F. Wong, Muzhou Shao, Li-Da Huang
    I/O Clustering in Design Cost and Performance Optimization for Flip-Chip Design. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:562-567 [Conf]
  8. I-Min Liu, Adnan Aziz
    Delay Constrained Optimization by Simultaneous Fanout Tree Construction, Buffer Insertion/Sizing and Gate Sizing. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:209-214 [Conf]
  9. I-Min Liu, Adnan Aziz, D. F. Wong, Hai Zhou
    An Efficient Buffer Insertion Algorithm for Large Networks Based on Lagrangian Relaxation. [Citation Graph (0, 0)][DBLP]
    ICCD, 1999, pp:210-215 [Conf]
  10. I-Min Liu, Tan-Li Chou, Adnan Aziz, D. F. Wong
    Zero-skew clock tree construction by simultaneous routing, wire sizing and buffer insertion. [Citation Graph (0, 0)][DBLP]
    ISPD, 2000, pp:33-38 [Conf]
  11. Hua Xiang, I-Min Liu, Martin D. F. Wong
    Wire Planning with Bounded Over-the-Block Wires. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:622-627 [Conf]
  12. Hung-Ming Chen, Li-Da Huang, I-Min Liu, Martin D. F. Wong
    Simultaneous power supply planning and noise avoidance in floorplan design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:4, pp:578-587 [Journal]
  13. Hung-Ming Chen, I-Min Liu, Martin D. F. Wong
    I/O Clustering in Design Cost and Performance Optimization for Flip-Chip Design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:11, pp:2552-2556 [Journal]
  14. Li-Da Huang, Xiaoping Tang, Hua Xiang, Martin D. F. Wong, I-Min Liu
    A polynomial time-optimal diode insertion/routing algorithm for fixing antenna problem [IC layout]. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:1, pp:141-147 [Journal]
  15. Hai Zhou, Martin D. F. Wong, I-Min Liu, Adnan Aziz
    Simultaneous routing and buffer insertion with restrictions onbuffer locations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:7, pp:819-824 [Journal]

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