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Tan-Li Chou :
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I-Min Liu , Hung-Ming Chen , Tan-Li Chou , Adnan Aziz , D. F. Wong Integrated power supply planning and floorplanning. [Citation Graph (0, 0)][DBLP ] ASP-DAC, 2001, pp:589-594 [Conf ] Zhanping Chen , Kaushik Roy , Tan-Li Chou Power sensitivity - a new method to estimate power dissipation considering uncertain specifications of primary inputs. [Citation Graph (0, 0)][DBLP ] ICCAD, 1997, pp:40-44 [Conf ] Tan-Li Chou , Kaushik Roy Statistical estimation of sequential circuit activity. [Citation Graph (0, 0)][DBLP ] ICCAD, 1995, pp:34-37 [Conf ] Tan-Li Chou , Kaushik Roy , Sharat Prasad Estimation of circuit activity considering signal correlations and simultaneous switching. [Citation Graph (0, 0)][DBLP ] ICCAD, 1994, pp:300-303 [Conf ] Tan-Li Chou , Kaushik Roy Estimation of sequential circuit activity considering spatial and temporal correlations. [Citation Graph (0, 0)][DBLP ] ICCD, 1995, pp:577-0 [Conf ] I-Min Liu , Tan-Li Chou , Adnan Aziz , D. F. Wong Zero-skew clock tree construction by simultaneous routing, wire sizing and buffer insertion. [Citation Graph (0, 0)][DBLP ] ISPD, 2000, pp:33-38 [Conf ] P. Patil , Tan-Li Chou , Kaushik Roy , R. Roy Low-Power Driven Logic Synthesis Using Accurate Power Estimation Technique. [Citation Graph (0, 0)][DBLP ] VLSI Design, 1997, pp:179-184 [Conf ] Hendrawan Soeleman , Kaushik Roy , Tan-Li Chou Estimating Circuit Activity in Combinational CMOS Digital Circuits. [Citation Graph (0, 0)][DBLP ] IEEE Design & Test of Computers, 2000, v:17, n:2, pp:112-119 [Journal ] Tan-Li Chou , Kaushik Roy Estimation of activity for static and domino CMOS circuits considering signal correlations and simultaneous switching. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:10, pp:1257-1265 [Journal ] Tan-Li Chou , Kaushik Roy Accurate power estimation of CMOS sequential circuits. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 1996, v:4, n:3, pp:369-380 [Journal ] Zhanping Chen , Kaushik Roy , Tan-Li Chou Efficient statistical approach to estimate power considering uncertain properties of primary inputs. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 1998, v:6, n:3, pp:484-492 [Journal ] Search in 0.002secs, Finished in 0.003secs