The SCEAS System
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## Search the dblp DataBase
Xuan Zeng:
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## Publications of Author- Bang Liu, Xuan Zeng, Yangfeng Su, Jun Tao, Zhaojun Bai, Charles Chiang, Dian Zhou
**Block SAPOR: block Second-order Arnoldi method for Passive Order Reduction of multi-input multi-output RCS interconnect circuits.**[Citation Graph (0, 0)][DBLP] ASP-DAC, 2005, pp:244-249 [Conf] - Jian Wang, Jun Tao, Xuan Zeng, Charles Chiang, Dian Zhou
**Analog circuit behavioral modeling via wavelet collocation method with auto-companding.**[Citation Graph (0, 0)][DBLP] ASP-DAC, 2004, pp:45-50 [Conf] - Xuan Zeng, Bank Liu, Jun Tao, Charles Chiang, Dian Zhou
**A novel wavelet method for noise analysis of nonlinear circuits.**[Citation Graph (0, 0)][DBLP] ASP-DAC, 2005, pp:471-476 [Conf] - Lihong Feng, Xuan Zeng, Charles Chiang, Dian Zhou, Qiang Fang
**Direct Nonlinear Order Reduction with Variational Analysis.**[Citation Graph (0, 0)][DBLP] DATE, 2004, pp:1316-1321 [Conf] - Xuan Zeng, Lihong Feng, Yangfeng Su, Wei Cai, Dian Zhou, Charles Chiang
**Time domain model order reduction by wavelet collocation method.**[Citation Graph (0, 0)][DBLP] DATE, 2006, pp:21-26 [Conf] - Xin Zhou, Dian Zhou, Jin Liu, Ruiming Li, Xuan Zeng, Charles Chiang
**Steady-State Analysis of Nonlinear Circuits Using Discrete Singular Convolution Method.**[Citation Graph (0, 0)][DBLP] DATE, 2004, pp:1322-1326 [Conf] - Ruiming Li, Dian Zhou, Jin Liu, Xuan Zeng
**Power-Optimal Simultaneous Buffer Insertion/Sizing and Wire Sizing.**[Citation Graph (0, 0)][DBLP] ICCAD, 2003, pp:581-587 [Conf] - Xin Li, Xuan Zeng, Dian Zhou, Xieting Ling
**Behavioral Modeling of Analog Circuits by Wavelet Collocation Method.**[Citation Graph (0, 0)][DBLP] ICCAD, 2001, pp:65-69 [Conf] - Yangfeng Su, Jian Wang, Xuan Zeng, Zhaojun Bai, Charles Chiang, Dian Zhou
**SAPOR: second-order Arnoldi method for passive order reduction of RCS circuits.**[Citation Graph (0, 0)][DBLP] ICCAD, 2004, pp:74-79 [Conf] - Lihong Feng, Xuan Zeng, Jiarong Tong, Charles Chiang, Dian Zhou
**Two-sided projection method in variational equation model order reduction of nonlinear circuits.**[Citation Graph (0, 0)][DBLP] ISCAS (4), 2004, pp:816-819 [Conf] - Ruiming Li, Dian Zhou, Jin Liu, Xuan Zeng
**Power-optimal simultaneous buffer insertion/sizing and uniform wire sizing for single long wires.**[Citation Graph (0, 0)][DBLP] ISCAS (1), 2005, pp:113-116 [Conf] - Jian Wang, Xuan Zeng, Wei Cai, Charles Chiang, Jiarong Tong, Dian Zhou
**Frequency domain wavelet method with GMRES for large-scale linear circuit simulation.**[Citation Graph (0, 0)][DBLP] ISCAS (5), 2004, pp:321-324 [Conf] - Xuan Zeng, Sheng Huang, Yangfeng Su, Dian Zhou
**An efficient Sylvester equation solver for time domain circuit simulation by wavelet collocation method.**[Citation Graph (0, 0)][DBLP] ISCAS (4), 2003, pp:664-667 [Conf] - Xuan Zeng, Jun Tao, Yangfeng Su, Wenbing Chen, Dian Zhou
**An error distribution based nonlinear companding method for analog behavioral modeling via wavelet approximation.**[Citation Graph (0, 0)][DBLP] ISCAS (3), 2003, pp:168-171 [Conf] - Xin Li, Bo Hu, Xieting Ling, Xuan Zeng
**A wavelet balance approach for steady-state analysis of nonlinear circuits.**[Citation Graph (0, 0)][DBLP] ISCAS (3), 2001, pp:73-76 [Conf] - Xin Li, Xuan Zeng, Dian Zhou, Xieting Ling
**Wavelet method for high-speed clock tree simulation.**[Citation Graph (0, 0)][DBLP] ISCAS (1), 2002, pp:177-180 [Conf] - Ruiming Li, Dian Zhou, Jin Liu, Xuan Zeng
**Power-optimal simultaneous buffer insertion/sizing and wire sizing for two-pin nets.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:12, pp:1915-1924 [Journal] - Hengliang Zhu, Xuan Zeng, Wei Cai, Jintao Xue, Dian Zhou
**A sparse grid based spectral stochastic collocation method for variations-aware capacitance extraction of interconnects under nanometer process technology.**[Citation Graph (0, 0)][DBLP] DATE, 2007, pp:1514-1519 [Conf] - Fan Yang, Xuan Zeng, Yangfeng Su, Dian Zhou
**RLCSYN: RLC Equivalent Circuit Synthesis for Structure-Preserved Reduced-order Model of Interconnect.**[Citation Graph (0, 0)][DBLP] ISCAS, 2007, pp:2710-2713 [Conf] - Jun Tao, Xuan Zeng, Fan Yang, Yangfeng Su, Lihong Feng, Wei Cai, Dian Zhou, Charles Chiang
**A one-shot projection method for interconnects with process variations.**[Citation Graph (0, 0)][DBLP] ISCAS, 2006, pp:- [Conf] **Statistical analysis of on-chip power grid networks by variational extended truncated balanced realization method.**[Citation Graph (, )][DBLP]**Stochastic Sparse-grid Collocation Algorithm (SSCA) for Periodic Steady-State Analysis of Nonlinear System with Process Variations.**[Citation Graph (, )][DBLP]**WCOMP: Waveform Comparison Tool for Mixed-signal Validation Regression in Memory Design.**[Citation Graph (, )][DBLP]**Robust Analog Circuit Sizing Using Ellipsoid Method and Affine Arithmetic.**[Citation Graph (, )][DBLP]**Timing yield driven clock skew scheduling considering non-Gaussian distributions of critical path delays.**[Citation Graph (, )][DBLP]**Multicore parallel min-cost flow algorithm for CAD applications.**[Citation Graph (, )][DBLP]**Provably good and practically efficient algorithms for CMP dummy fill.**[Citation Graph (, )][DBLP]**Statistical reliability analysis under process variation and aging effects.**[Citation Graph (, )][DBLP]**Global routing and track assignment for flip-chip designs.**[Citation Graph (, )][DBLP]**An efficient transistor-level piecewise-linear macromodeling approach for model order reduction of nonlinear circuits.**[Citation Graph (, )][DBLP]**Parameterized model order reduction via a two-directional Arnoldi process.**[Citation Graph (, )][DBLP]**Binning optimization based on SSTA for transparently-latched circuits.**[Citation Graph (, )][DBLP]**Characterizing Intra-Die Spatial Correlation Using Spectral Density Method.**[Citation Graph (, )][DBLP]**Adaptive Stochastic Collocation Method (ASCM) for Parameterized Statistical Timing Analysis with Quadratic Delay Model.**[Citation Graph (, )][DBLP]**A Spectral Stochastic Collocation Method for Capacitance Extraction of Interconnects with Process Variations.**[Citation Graph (, )][DBLP]**The Study on the Electric Network Planning Problem Based on the Ant Colony-Simulated Annealing Algorithm.**[Citation Graph (, )][DBLP]**The design of Three Gorges water environment risk and early warning platform based on GIS technology.**[Citation Graph (, )][DBLP]
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