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Title:
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Charles Chiang: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Bang Liu, Xuan Zeng, Yangfeng Su, Jun Tao, Zhaojun Bai, Charles Chiang, Dian Zhou
    Block SAPOR: block Second-order Arnoldi method for Passive Order Reduction of multi-input multi-output RCS interconnect circuits. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:244-249 [Conf]
  2. Jian Wang, Jun Tao, Xuan Zeng, Charles Chiang, Dian Zhou
    Analog circuit behavioral modeling via wavelet collocation method with auto-companding. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:45-50 [Conf]
  3. Xuan Zeng, Bank Liu, Jun Tao, Charles Chiang, Dian Zhou
    A novel wavelet method for noise analysis of nonlinear circuits. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:471-476 [Conf]
  4. Jianfeng Luo, Subarna Sinha, Qing Su, Jamil Kawa, Charles Chiang
    An IC manufacturing yield model considering intra-die variations. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:749-754 [Conf]
  5. Charles Chiang, Andrew B. Kahng, Subarna Sinha, Xu Xu, Alexander Zelikovsky
    Bright-Field AAPSM Conflict Detection and Correction. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:908-913 [Conf]
  6. Lihong Feng, Xuan Zeng, Charles Chiang, Dian Zhou, Qiang Fang
    Direct Nonlinear Order Reduction with Variational Analysis. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1316-1321 [Conf]
  7. Xuan Zeng, Lihong Feng, Yangfeng Su, Wei Cai, Dian Zhou, Charles Chiang
    Time domain model order reduction by wavelet collocation method. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:21-26 [Conf]
  8. Xin Zhou, Dian Zhou, Jin Liu, Ruiming Li, Xuan Zeng, Charles Chiang
    Steady-State Analysis of Nonlinear Circuits Using Discrete Singular Convolution Method. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1322-1326 [Conf]
  9. Wen Yujie, Jiarong Tong, Charles Chiang
    Domain Specific Non-Uniform Routing Architecture for Embedded Programmable IP Core (abstract only). [Citation Graph (0, 0)][DBLP]
    FPGA, 2005, pp:269- [Conf]
  10. Charles Chiang, Qing Su, Ching-Shoei Chiang
    Wirelength reduction by using diagonal wire. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2003, pp:104-107 [Conf]
  11. Dan Page, Jamil Kawa, Charles Chiang
    DFM: swimming upstream. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:1- [Conf]
  12. Jamil Kawa, Charles Chiang
    DFM issues for 65nm and beyond. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:318-322 [Conf]
  13. Charles Chiang, Andrew B. Kahng, Subarna Sinha, Xu Xu
    Fast and efficient phase conflict detection and correction in standard-cell layouts. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:149-156 [Conf]
  14. Jianfeng Luo, Qing Su, Charles Chiang, Jamil Kawa
    A layout dependent full-chip copper electroplating topography model. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:133-140 [Conf]
  15. Yangfeng Su, Jian Wang, Xuan Zeng, Zhaojun Bai, Charles Chiang, Dian Zhou
    SAPOR: second-order Arnoldi method for passive order reduction of RCS circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:74-79 [Conf]
  16. H. Yao, S. Sinha, C. Chiang, X. Hong, Y. Cai
    Efficient process-hotspot detection using range pattern matching. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:625-632 [Conf]
  17. Bo-Kyung Choi, Charles Chiang, Jamil Kawa, Majid Sarrafzadeh
    Routing resources consumption on M-arch and X-arch. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2004, pp:73-76 [Conf]
  18. Lihong Feng, Xuan Zeng, Jiarong Tong, Charles Chiang, Dian Zhou
    Two-sided projection method in variational equation model order reduction of nonlinear circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2004, pp:816-819 [Conf]
  19. Jian Wang, Xuan Zeng, Wei Cai, Charles Chiang, Jiarong Tong, Dian Zhou
    Frequency domain wavelet method with GMRES for large-scale linear circuit simulation. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2004, pp:321-324 [Conf]
  20. Xin Wang, Charles Chiang, Jamil Kawa, Qing Su
    A Min-Variance Iterative Method for Fast Smart Dummy Feature Density Assignment in Chemical-Mechanical Polishing. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:258-263 [Conf]
  21. Subarna Sinha, Qing Su, Linni Wen, Frank Lee, Charles Chiang, Yi-Kan Cheng, Jin-Lien Lin, Yu-Chyi Harn
    A New Flexible Algorithm for Random Yield Improvement. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:795-800 [Conf]
  22. Charles Chiang, Majid Sarrafzadeh, Chak-Kuen Wong
    Global routing based on Steiner min-max trees. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:12, pp:1318-1325 [Journal]
  23. Charles Chiang, Chak-Kuen Wong, Majid Sarrafzadeh
    A weighted Steiner tree-based global router with simultaneous length and density minimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:12, pp:1461-1469 [Journal]
  24. Qing Su, Jamil Kawa, Charles Chiang, Yehia Massoud
    Accurate modeling of substrate resistive coupling for floating substrates. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2006, v:11, n:1, pp:44-51 [Journal]
  25. Jun Tao, Xuan Zeng, Fan Yang, Yangfeng Su, Lihong Feng, Wei Cai, Dian Zhou, Charles Chiang
    A one-shot projection method for interconnects with process variations. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  26. Charles Chiang, Andrew B. Kahng, Subarna Sinha, Xu Xu, Alexander Zelikovsky
    Bright-Field AAPSM Conflict Detection and Correction [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]

  27. The road to 3D EDA tool readiness. [Citation Graph (, )][DBLP]


  28. Model Based Layout Pattern Dependent Metal Filling Algorithm for Improved Chip Surface Uniformity in the Copper Process. [Citation Graph (, )][DBLP]


  29. Stochastic Sparse-grid Collocation Algorithm (SSCA) for Periodic Steady-State Analysis of Nonlinear System with Process Variations. [Citation Graph (, )][DBLP]


  30. A methodology for fast and accurate yield factor estimation during global routing. [Citation Graph (, )][DBLP]


  31. Accurate detection for process-hotspots with vias and incomplete specification. [Citation Graph (, )][DBLP]


  32. Hotspot Based Yield Prediction with Consideration of Correlations. [Citation Graph (, )][DBLP]


  33. Three DFM Challenges: Random Defects, Thickness Variation, and Printability Variation. [Citation Graph (, )][DBLP]


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