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Mohammad Hosseinabady: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Pejman Lotfi-Kamran, Mohammad Hosseinabady, Hamid Shojaei, Mehran Massoumi, Zainalabedin Navabi
    TED+: a data structure for microprocessor verification. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:567-572 [Conf]
  2. Mohammad Hosseinabady, Abbas Banaiyan, Mahdi Nazm Bojnordi, Zainalabedin Navabi
    A concurrent testing method for NoC switches. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1171-1176 [Conf]
  3. Shervin Sharifi, Javid Jaffari, Mohammad Hosseinabady, Ali Afzali-Kusha, Zainalabedin Navabi
    Simultaneous Reduction of Dynamic and Static Power in Scan Structures. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:846-851 [Conf]
  4. Shervin Sharifi, Mohammad Hosseinabady, Pedram A. Riahi, Zainalabedin Navabi
    Reducing Test Power, Time and Data Volume in SoC Testing Using Selective Trigger Scan Architecture. [Citation Graph (0, 0)][DBLP]
    DFT, 2003, pp:352-360 [Conf]
  5. Shervin Sharifi, Mohammad Hosseinabady, Zainalabedin Navabi
    Selective Trigger Scan Architecture for Reducing Power, Time and Data Volume in SoC Testing. [Citation Graph (0, 0)][DBLP]
    VLSI-SOC, 2003, pp:215-220 [Conf]
  6. Mohammad Hosseinabady, Mohammad Hossein Neishaburi, Pejman Lotfi-Kamran, Zainalabedin Navabi
    A UML Based System Level Failure Rate Assessment Technique for SoC Designs. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:243-248 [Conf]
  7. Mohammad Hosseinabady, Atefe Dalirsani, Zainalabedin Navabi
    Using the inter- and intra-switch regularity in NoC switch testing. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:361-366 [Conf]
  8. Atefe Dalirsani, Mohammad Hosseinabady, Zainalabedin Navabi
    An Analytical Model for Reliability Evaluation of NoC Architectures. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2007, pp:49-56 [Conf]
  9. Mohammad Hosseinabady, Mohammad Hossein Neishaburi, Zainalabedin Navabi, Alfredo Benso, Stefano Di Carlo, Paolo Prinetto, Giorgio Di Natale
    Analysis of System-Failure Rate Caused by Soft-Errors using a UML-Based Systematic Methodology in an SoC. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2007, pp:205-206 [Conf]
  10. Mohammad Hosseinabady, Pejman Lotfi-Kamran, Giorgio Di Natale, Stefano Di Carlo, Alfredo Benso, Paolo Prinetto
    Single-Event Upset Analysis and Protection in High Speed Circuits. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2006, pp:29-34 [Conf]
  11. Shervin Sharifi, Javid Jaffari, Mohammad Hosseinabady, Ali Afzali-Kusha, Zainalabedin Navabi
    Simultaneous Reduction of Dynamic and Static Power in Scan Structures [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  12. Mohammad Hosseinabady, Pejman Lotfi-Kamran, Zainalabedin Navabi
    Low test application time resource binding for behavioral synthesis. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2007, v:12, n:2, pp:- [Journal]
  13. Shervin Sharifi, Javid Jaffari, Mohammad Hosseinabady, Ali Afzali-Kusha, Zainalabedin Navabi
    Scan-Based Structure with Reduced Static and Dynamic Power Consumption. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2006, v:2, n:3, pp:477-487 [Journal]

  14. Fault-tolerant dynamically reconfigurable NoC-based SoC. [Citation Graph (, )][DBLP]


  15. Single Event Upset Detection and Correction. [Citation Graph (, )][DBLP]


  16. De Bruijn Graph as a Low Latency Scalable Architecture for Energy Efficient Massive NoCs. [Citation Graph (, )][DBLP]


  17. Run-time resource management in fault-tolerant network on reconfigurable chips. [Citation Graph (, )][DBLP]


  18. Fault tolerant bit parallel finite field multipliers using LDPC codes. [Citation Graph (, )][DBLP]


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