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Jinan Lou: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Jinan Lou, Amir H. Salek, Massoud Pedram
    An Integrated Flow for Technology Remapping and Placement of Sub-half-micron Circuits. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1998, pp:295-300 [Conf]
  2. Amir H. Salek, Jinan Lou, Massoud Pedram
    A DSM Design Flow: Putting Floorplanning, Technology-Napping, and Gate-Placement Together. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:128-134 [Conf]
  3. Amir H. Salek, Jinan Lou, Massoud Pedram
    MERLIN: Semi-Order-Independent Hierarchical Buffered Routing Tree Generation Using Local Neighborhood Search. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:472-478 [Conf]
  4. Jinan Lou, Wei Chen, Massoud Pedram
    Concurrent logic restructuring and placement for timing closure. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:31-36 [Conf]
  5. Jinan Lou, Amir H. Salek, Massoud Pedram
    An exact solution to simultaneous technology mapping and linear placement problem. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:671-675 [Conf]
  6. Amir H. Salek, Jinan Lou, Massoud Pedram
    A simultaneous routing tree construction and fanout optimization algorithm. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:625-630 [Conf]
  7. Jinan Lou, Shankar Krishnamoorthy, Henry S. Sheng
    Estimating routing congestion using probabilistic analysis. [Citation Graph (0, 0)][DBLP]
    ISPD, 2001, pp:112-117 [Conf]
  8. Jinan Lou, Wei Chen
    Crosstalk-Aware Placement. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2004, v:21, n:1, pp:24-32 [Journal]
  9. Jinan Lou, Shashidhar Thakur, Shankar Krishnamoorthy, Henry S. Sheng
    Estimating routing congestion using probabilistic analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:1, pp:32-41 [Journal]
  10. Amir H. Salek, Jinan Lou, Massoud Pedram
    An integrated logical and physical design flow for deep submicron circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:9, pp:1305-1315 [Journal]
  11. Amir H. Salek, Jinan Lou, Massoud Pedram
    Hierarchical buffered routing tree generation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:5, pp:554-567 [Journal]

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