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José C. Monteiro: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. José C. Monteiro, Arlindo L. Oliveira
    FSM decomposition by direct circuit manipulation applied to low power design. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:351-358 [Conf]
  2. José C. Monteiro, Srinivas Devadas, Bill Lin
    A Methodology for Efficient Estimation of Switching Activity in Sequential Logic Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:12-17 [Conf]
  3. José C. Monteiro, Arlindo L. Oliveira
    Finite State Machine Decomposition For Low Power. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:758-763 [Conf]
  4. Mazhar Alidina, José C. Monteiro, Srinivas Devadas, Abhijit Ghosh, Marios C. Papaefthymiou
    Precomputation-based sequential logic optimization for low power. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:74-81 [Conf]
  5. Paulo F. Flores, José C. Monteiro, Eduardo A. C. da Costa
    An exact algorithm for the maximal sharing of partial terms in multiple constant multiplications. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:13-16 [Conf]
  6. José C. Monteiro, Srinivas Devadas, Abhijit Ghosh
    Retiming sequential circuits for low power. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:398-402 [Conf]
  7. Antônio Mota, Nuno Ferreira, Arlindo L. Oliveira, José C. Monteiro
    Integrating Dynamic Power Management in the Design Flow. [Citation Graph (0, 0)][DBLP]
    VLSI, 1999, pp:233-244 [Conf]
  8. José C. Costa, José C. Monteiro, Srinivas Devadas
    Switching activity estimation using limited depth reconvergent path analysis. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1997, pp:184-189 [Conf]
  9. Vagner S. Rosa, Eduardo A. C. da Costa, José C. Monteiro, Sergio Bampi
    An improved synthesis method for low power hardwired FIR filters. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2004, pp:237-241 [Conf]
  10. M. Fonseca, Eduardo A. C. da Costa, Sergio Bampi, José C. Monteiro
    Design of a radix-2m hybrid array multiplier using carry save adder format. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2005, pp:172-177 [Conf]
  11. Eduardo A. C. da Costa, Sergio Bampi, José C. Monteiro
    A New Pipelined Array Architecture for Signed Multiplication. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2003, pp:65-70 [Conf]
  12. Srinivas Devadas, Sharad Malik, José C. Monteiro, Luciano Lavagno
    CAD Techniques for Embedded System Design. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:608- [Conf]
  13. Paulo F. Flores, José C. Costa, Horácio C. Neto, José C. Monteiro, João P. Marques Silva
    Assignment and Reordering of Incompletely Specified Pattern Sequences Targetting Minimum Power Dissipation. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:37-41 [Conf]
  14. José C. Monteiro, James H. Kukula, Srinivas Devadas, Horácio C. Neto
    Bitwise Encoding of Finite State Machines. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:379-382 [Conf]
  15. Eduardo A. C. da Costa, José C. Monteiro, Sergio Bampi
    A new array architecture for signed multiplication using Gray encoded radix-2m operands. [Citation Graph (0, 0)][DBLP]
    Integration, 2007, v:40, n:2, pp:118-132 [Journal]
  16. José C. Monteiro, Srinivas Devadas, Abhijit Ghosh
    Sequential logic optimization for low power using input-disabling precomputation architectures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:3, pp:279-284 [Journal]
  17. José C. Monteiro, Srinivas Devadas, Abhijit Ghosh, Kurt Keutzer, Jacob K. White
    Estimation of average switching activity in combinational logic circuits using symbolic simulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:1, pp:121-127 [Journal]
  18. Levent Aksoy, Eduardo A. C. da Costa, Paulo F. Flores, José C. Monteiro
    Optimization of Area in Digital FIR Filters using Gate-Level Metrics. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:420-423 [Conf]
  19. Leonardo L. de Oliveira, Cristiano Santos, Daniel Lima Ferrão, Eduardo A. C. da Costa, José C. Monteiro, João Baptista Martins, Sergio Bampi, Ricardo Augusto da Luz Reis
    A Comparison of Layout Implementations of Pipelined and Non-Pipelined Signed Radix-4 Array Multiplier and Modified Booth Multiplier Architectures. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2005, pp:25-39 [Conf]
  20. Chi-Ying Tsui, José C. Monteiro, Massoud Pedram, Srinivas Devadas, Alvin M. Despain, Bill Lin
    Power estimation methods for sequential logic circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1995, v:3, n:3, pp:404-416 [Journal]
  21. Chi-Ying Tsui, José C. Monteiro, Massoud Pedram, Srinivas Devadas, Alvin M. Despain, Bill Lin
    Correction to "Power Estimation Methods for Sequential Logic Circuits" [Correspondence]. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1996, v:4, n:4, pp:495- [Journal]
  22. José C. Monteiro, Arlindo L. Oliveira
    Implicit FSM decomposition applied to low-power design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:5, pp:560-565 [Journal]

  23. A MILP-based approach to path sensitization of embedded software. [Citation Graph (, )][DBLP]


  24. Parameter tuning in SVM-based power macro-modeling. [Citation Graph (, )][DBLP]


  25. Generating Worst-Case Stimuli for Accurate Power Grid Analysis. [Citation Graph (, )][DBLP]


  26. Analysis of Power Consumption Using a New Methodology for the Capacitance Modeling of Complex Logic Gates. [Citation Graph (, )][DBLP]


  27. Effect of Number Representation on the Achievable Minimum Number of Operations in Multiple Constant Multiplications. [Citation Graph (, )][DBLP]


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