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Bo Yao :
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Makoto Mori , Hongyu Chen , Bo Yao , Chung-Kuan Cheng A multiple level network approach for clock skew minimization with process variations. [Citation Graph (0, 0)][DBLP ] ASP-DAC, 2004, pp:263-268 [Conf ] Shuo Zhou , Bo Yao , Hongyu Chen , Yi Zhu , Chung-Kuan Cheng , Michael Hutton Efficient static timing analysis using a unified framework for false paths and multi-cycle paths. [Citation Graph (0, 0)][DBLP ] ASP-DAC, 2006, pp:73-78 [Conf ] Shuo Zhou , Bo Yao , Jianhua Liu , Chung-Kuan Cheng Integrated algorithmic logical and physical design of integer multiplier. [Citation Graph (0, 0)][DBLP ] ASP-DAC, 2005, pp:1014-1017 [Conf ] Hongyu Chen , Chung-Kuan Cheng , Nan-Chi Chou , Andrew B. Kahng , John F. MacDonald , Peter Suaris , Bo Yao , Zhengyong Zhu An algebraic multigrid solver for analytical placement with layout based clustering. [Citation Graph (0, 0)][DBLP ] DAC, 2003, pp:794-799 [Conf ] Zhengyong Zhu , Bo Yao , Chung-Kuan Cheng Power network analysis using an adaptive algebraic multigrid approach. [Citation Graph (0, 0)][DBLP ] DAC, 2003, pp:105-108 [Conf ] Hongyu Chen , Chung-Kuan Cheng , Andrew B. Kahng , Ion I. Mandoiu , Qinke Wang , Bo Yao The Y-Architecture for On-Chip Interconnect: Analysis and Methodology. [Citation Graph (0, 0)][DBLP ] ICCAD, 2003, pp:13-20 [Conf ] Shuo Zhou , Bo Yao , Hongyu Chen , Yi Zhu , Chung-Kuan Cheng , Michael Hutton , Truman Collins , Sridhar Srinivasan , Nan-Chi Chou , Peter Suaris Improving the efficiency of static timing analysis with false paths. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:527-531 [Conf ] Hongyu Chen , Bo Yao , Feng Zhou , Chung-Kuan Cheng Physical Planning Of On-Chip Interconnect Architectures. [Citation Graph (0, 0)][DBLP ] ICCD, 2002, pp:30-35 [Conf ] Esther Y. Cheng , Feng Zhou , Bo Yao , Chung-Kuan Cheng , Ronald L. Graham Balancing the Interconnect Topology for Arrays of Processors between Cost and Power. [Citation Graph (0, 0)][DBLP ] ICCD, 2002, pp:180-186 [Conf ] Bo Yao , Hongyu Chen , Chung-Kuan Cheng , Nan-Chi Chou , Lung-Tien Liu , Peter Suaris Unified quadratic programming approach for mixed mode placement. [Citation Graph (0, 0)][DBLP ] ISPD, 2005, pp:193-199 [Conf ] Bo Yao , Hongyu Chen , Chung-Kuan Cheng , Ronald L. Graham Revisiting floorplan representations. [Citation Graph (0, 0)][DBLP ] ISPD, 2001, pp:138-143 [Conf ] Ling Zhang , Hongyu Chen , Bo Yao , Kevin Hamilton , Chung-Kuan Cheng Repeated On-Chip Interconnect Analysis and Evaluation of Delay, Power, and Bandwidth Metrics under Different Design Goals. [Citation Graph (0, 0)][DBLP ] ISQED, 2007, pp:251-256 [Conf ] Feng Zhou , Esther Y. Cheng , Bo Yao , Chung-Kuan Cheng , Ronald L. Graham A hierarchical three-way interconnect architecture for hexagonal processors. [Citation Graph (0, 0)][DBLP ] SLIP, 2003, pp:133-139 [Conf ] Hongyu Chen , Chung-Kuan Cheng , Andrew B. Kahng , Ion I. Mandoiu , Qinke Wang , Bo Yao The Y architecture for on-chip interconnect: analysis and methodology. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:4, pp:588-599 [Journal ] Bo Yao , Hongyu Chen , Chung-Kuan Cheng , Ronald L. Graham Floorplan representations: Complexity and connections. [Citation Graph (0, 0)][DBLP ] ACM Trans. Design Autom. Electr. Syst., 2003, v:8, n:1, pp:55-80 [Journal ] Deterministic broadside test generation for transition path delay faults. [Citation Graph (, )][DBLP ] CacheCompress: a novel approach for test data compression with cache for IP embedded cores. [Citation Graph (, )][DBLP ] Research on ANN-based model of joint collocation of water quantity and quality. [Citation Graph (, )][DBLP ] On the Temporal-Spatial Correlation Based Fault-Tolerant Dynamic Event Region Detection Scheme in Wireless Sensor Networks. [Citation Graph (, )][DBLP ] Adaptive Defogging of a Single Image. [Citation Graph (, )][DBLP ] Search in 0.002secs, Finished in 0.301secs