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Publications of Author

1. Takashi Morimoto, Yohmei Harada, Tetsushi Koide, Hans Jürgen Mattausch
   350nm CMOS test-chip for architecture verification of real-time QVGA color-video segmentation at the 90nm technology node. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2004, pp:531-532 [Conf]
   
2. Takashi Morimoto, Osamu Kiriyama, Hidekazu Adachi, Zhaomin Zhu, Tetsushi Koide, Hans Jürgen Mattausch
   A low-power video segmentation LSI with boundary-active-only architecture. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2005, pp:13-14 [Conf]
   
3. D. Miyawaki, S. Matsumoto, Hans Jürgen Mattausch, S. Ooshiro, M. Suetake, Michiko Miura-Mattausch, Shigetaka Kumashiro, T. Yamaguchi, K. Yamashita, N. Nakayama
   Correlation method of circuit-performance and technology fluctuations for improved design reliability. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2001, pp:39-44 [Conf]
   
4. Tetsuya Sueyoshi, Hiroshi Uchida, Hans Jürgen Mattausch, Tetsushi Koide, Yosuke Mitani, Tetsuo Hironaka
   Compact 12-port multi-bank register file test-chip in 0.35µm CMOS for highly parallel processors. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2004, pp:551-552 [Conf]
   
5. M. Tanaka, N. Tokida, T. Okagaki, Michiko Miura-Mattausch, Walter Hansch, Hans Jürgen Mattausch
   High performance of short-channel MOSFETs due to an elevated central-channel doping. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2000, pp:365-370 [Conf]
   
6. K. Yamaoka, Takashi Morimoto, Hidekazu Adachi, Tetsushi Koide, Hans Jürgen Mattausch
   Image segmentation and pattern matching based FPGA/ASIC implementation architecture of real-time object tracking. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2006, pp:176-181 [Conf]
   
7. Yuji Yano, Tetsushi Koide, Hans Jürgen Mattausch
   Associative memory with fully parallel nearest-Manhattan-distance search for low-power real-time single-chip applications. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2004, pp:543-544 [Conf]
   
8. Takeshi Kumaki, Yasuto Kuroda, Tetsushi Koide, Hans Jürgen Mattausch, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito
   CAM-based VLSI architecture for Huffman coding with real-time optimization of the code word table [image coding example]. [Citation Graph (0, 0)][DBLP]
   ISCAS (5), 2005, pp:5202-5205 [Conf]
   
9. Takahiro Sasaki, Tomohiro Inoue, Nobuhiko Omori, Tetsuo Hironaka, Hans Jürgen Mattausch, Tetsushi Koide
   Chip size and performance evaluations of shared cache for on-chip multiprocessor. [Citation Graph (0, 0)][DBLP]
   Systems and Computers in Japan, 2005, v:36, n:9, pp:1-13 [Journal]
   
10. Takeshi Kumaki, Tetsushi Koide, Hans Jürgen Mattausch, Yasuto Kuroda, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito
    Efficient Vertical/Horizontal-Space 1D-DCT Processing Based on Massive-Parallel Matrix-Processing Engine. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:525-528 [Conf]
    
11. K. Yamaoka, Takashi Morimoto, Hidekazu Adachi, K. Awane, Tetsushi Koide, Hans Jürgen Mattausch
    Multi-object tracking VLSI architecture using image-scan based region growing and feature matching. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
    
12. 
    A parallel hardware design for parametric active contour models. [Citation Graph (, )][DBLP]
    
    
13. 
    Design of superscalar processor with multi-bank register file. [Citation Graph (, )][DBLP]
    
    
14. 
    Object tracking in video pictures based on image segmentation and pattern matching. [Citation Graph (, )][DBLP]
    
    
15. 
    Unified Data/Instruction Cache with Hierarchical Multi-Port Architecture and Hidden Precharge Pipeline. [Citation Graph (, )][DBLP]
    
    
16. 
    Fully Parallel Associative Memory Architecture with Mixed Digital-Analog Match Circuit for Nearest Euclidean Distance Search. [Citation Graph (, )][DBLP]
    
    
17. 
    Application of Multi-ported CAM for Parallel Coding. [Citation Graph (, )][DBLP]
    
    
18. 
    An FPGA-Based Region-Growing Video Segmentation System with Boundary-Scan-Only LSI Architecture. [Citation Graph (, )][DBLP]