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Jawahar Jain: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Rajarshi Mukherjee, Jawahar Jain, Koichiro Takayama, Masahiro Fujita
    Automatic partitioning for efficient combinatorial verification. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:67-72 [Conf]
  2. Subramanian K. Iyer, Jawahar Jain, Debashis Sahoo, Takeshi Shimizu
    Verification of Industrial Designs Using A Computing Grid With More than 100 Nodes. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2005, pp:460- [Conf]
  3. Debashis Sahoo, Jawahar Jain, Subramanian K. Iyer, David L. Dill
    A New Reachability Algorithm for Symmetric Multi-processor Architecture. [Citation Graph (0, 0)][DBLP]
    ATVA, 2005, pp:26-38 [Conf]
  4. Subramanian K. Iyer, Jawahar Jain, Mukul R. Prasad, Debashis Sahoo, Thomas Sidle
    Error Detection Using BMC in a Parallel Environment. [Citation Graph (0, 0)][DBLP]
    CHARME, 2005, pp:354-358 [Conf]
  5. Subramanian K. Iyer, Debashis Sahoo, Christian Stangier, Amit Narayan, Jawahar Jain
    Improved Symbolic Verification Using Partitioning Techniques. [Citation Graph (0, 0)][DBLP]
    CHARME, 2003, pp:410-424 [Conf]
  6. Debashis Sahoo, Jawahar Jain, Subramanian K. Iyer, David L. Dill, E. Allen Emerson
    Predictive Reachability Using a Sample-Based Approach. [Citation Graph (0, 0)][DBLP]
    CHARME, 2005, pp:388-392 [Conf]
  7. Vamsi Boppana, Rajarshi Mukherjee, Jawahar Jain, Masahiro Fujita, Pradeep Bollineni
    Multiple Error Diagnosis Based on Xlists. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:660-665 [Conf]
  8. Jawahar Jain, Rajarshi Mukherjee, Masahiro Fujita
    Advanced Verification Techniques Based on Learning. [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:420-426 [Conf]
  9. Jawahar Jain, K. Mohanram, Dinos Moundanos, Ingo Wegener, Yuan Lu
    Analysis of composition complexity and how to obtain smaller canonical graphs. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:681-686 [Conf]
  10. Yuan Lu, Jawahar Jain, Edmund M. Clarke, Masahiro Fujita
    Efficient variable ordering using aBDD based sampling. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:687-692 [Conf]
  11. Kelvin Ng, Mukul R. Prasad, Rajarshi Mukherjee, Jawahar Jain
    Solving the latch mapping problem in an industrial setting. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:442-447 [Conf]
  12. Debashis Sahoo, Jawahar Jain, Subramanian K. Iyer, David L. Dill, E. Allen Emerson
    Multi-threaded reachability. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:467-470 [Conf]
  13. Rajarshi Mukherjee, Jawahar Jain, Koichiro Takayama, Masahiro Fujita, Jacob A. Abraham, Donald S. Fussell
    An Efficient Filter-Based Approach for Combinational Verification. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:132-137 [Conf]
  14. Subramanian K. Iyer, Debashis Sahoo, E. Allen Emerson, Jawahar Jain
    On Partitioning and Symbolic Model Checking. [Citation Graph (0, 0)][DBLP]
    FM, 2005, pp:497-511 [Conf]
  15. Debashis Sahoo, Subramanian K. Iyer, Jawahar Jain, Christian Stangier, Amit Narayan, David L. Dill, E. Allen Emerson
    A Partitioning Methodology for BDD-Based Verification. [Citation Graph (0, 0)][DBLP]
    FMCAD, 2004, pp:399-413 [Conf]
  16. Jawahar Jain, Amit Narayan, C. Coelho, Sunil P. Khatri, Alberto L. Sangiovanni-Vincentelli, Robert K. Brayton, Masahiro Fujita
    Decomposition Techniques for Efficient ROBDD Construction. [Citation Graph (0, 0)][DBLP]
    FMCAD, 1996, pp:419-434 [Conf]
  17. James R. Bitner, Jawahar Jain, Magdy S. Abadir, Jacob A. Abraham, Donald S. Fussell
    Efficient Algorithmic Circuit Verification Using Indexed BDDs. [Citation Graph (0, 0)][DBLP]
    FTCS, 1994, pp:266-275 [Conf]
  18. Jawahar Jain, William Adams, Masahiro Fujita
    Sampling schemes for computing OBDD variable orderings. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:631-638 [Conf]
  19. Jawahar Jain, Jim Bitner, Donald S. Fussell, Jacob A. Abraham
    Probabilistic Design Verification. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:468-471 [Conf]
  20. Amit Narayan, Adrian J. Isles, Jawahar Jain, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    Reachability analysis using partitioned-ROBDDs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:388-393 [Conf]
  21. Amit Narayan, Jawahar Jain, Masahiro Fujita, Alberto L. Sangiovanni-Vincentelli
    Partitioned ROBDDs - a compact, canonical and efficiently manipulable representation for Boolean functions. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1996, pp:547-554 [Conf]
  22. Jawahar Jain, Amit Narayan, Masahiro Fujita, Alberto L. Sangiovanni-Vincentelli
    A Survey of Techniques for Formal Verification of Combinational Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 1997, pp:445-454 [Conf]
  23. Mukul R. Prasad, Michael S. Hsiao, Jawahar Jain
    Improving Sequential ATPG Using SAT Methods. [Citation Graph (0, 0)][DBLP]
    IWLS, 2002, pp:79-84 [Conf]
  24. Vamsi Boppana, Indradeep Ghosh, Rajarshi Mukherjee, Jawahar Jain, Masahiro Fujita
    Hierarchical Error Diagnosis Targeting RTL Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:436-441 [Conf]
  25. Jawahar Jain, Dinos Moundanos, James R. Bitner, Jacob A. Abraham, Donald S. Fussell, Don E. Ross
    Efficient variable ordering and partial representation algorithm. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:81-86 [Conf]
  26. Jawahar Jain, Amit Narayan, Masahiro Fujita, Alberto L. Sangiovanni-Vincentelli
    Formal Verification of Combinational Circuit. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:218-225 [Conf]
  27. Rajarshi Mukherjee, Jawahar Jain, Masahiro Fujita, Jacob A. Abraham, Donald S. Fussell
    On More Efficient Combinational ATPG Using Functional Learning. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1996, pp:107-110 [Conf]
  28. Rajeev Murgai, Jawahar Jain, Masahiro Fujita
    Efficient Scheduling Techniques for ROBDD Construction. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:394-401 [Conf]
  29. Amit Narayan, Sunil P. Khatri, Jawahar Jain, Masahiro Fujita, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
    A study of composition schemes for mixed apply/compose based construction of ROBDDs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1996, pp:249-253 [Conf]
  30. Mukul R. Prasad, Michael S. Hsiao, Jawahar Jain
    Can SAT be used to Improve Sequential ATPG Methods? [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:585-0 [Conf]
  31. Ankur Jain, Vamsi Boppana, Rajarshi Mukherjee, Jawahar Jain, Masahiro Fujita, Michael S. Hsiao
    Testing, Verification, and Diagnosis in the Presence of Unknowns. [Citation Graph (0, 0)][DBLP]
    VTS, 2000, pp:263-270 [Conf]
  32. Subramanian K. Iyer, Jawahar Jain, Debashis Sahoo, E. Allen Emerson
    Under-approximation Heuristics for Grid-based Bounded Model Checking. [Citation Graph (0, 0)][DBLP]
    Electr. Notes Theor. Comput. Sci., 2006, v:135, n:2, pp:31-46 [Journal]
  33. Jawahar Jain, Jacob A. Abraham, James R. Bitner, Donald S. Fussell
    Probabilistic Verification of Boolean Functions. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 1992, v:1, n:1, pp:61-115 [Journal]
  34. Rajarshi Mukherjee, Jawahar Jain, Koichiro Takayama, Jacob A. Abraham, Donald S. Fussell, Masahiro Fujita
    Efficient Combinational Verification Using Overlapping Local BDDs and a Hash Table. [Citation Graph (0, 0)][DBLP]
    Formal Methods in System Design, 2002, v:21, n:1, pp:95-101 [Journal]
  35. Jawahar Jain, James R. Bitner, Magdy S. Abadir, Jacob A. Abraham, Donald S. Fussell
    Indexed BDDs: Algorithmic Advances in Techniques to Represent and Verify Boolean Functions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1997, v:46, n:11, pp:1230-1245 [Journal]
  36. Jawahar Jain, Ingo Wegener, Masahiro Fujita
    A Note on Complexity of OBDD Composition and Efficiency of Partitioned-OBDDs over OBDDs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2001, v:50, n:11, pp:1289-1290 [Journal]
  37. Subramanian K. Iyer, Debashis Sahoo, E. Allen Emerson, Jawahar Jain
    On partitioning and symbolic model checking. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:5, pp:780-788 [Journal]
  38. Rajarshi Mukherjee, Jawahar Jain, Koichiro Takayama, Masahiro Fujita, Jacob A. Abraham, Donald S. Fussell
    An efficient filter-based approach for combinational verification. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:11, pp:1542-1557 [Journal]

  39. Dynamically resizable binary decision diagrams. [Citation Graph (, )][DBLP]


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