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Publications of Author

1. Rajarshi Mukherjee, Jawahar Jain, Koichiro Takayama, Masahiro Fujita
   Automatic partitioning for efficient combinatorial verification. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2000, pp:67-72 [Conf]
   
2. Vamsi Boppana, Sreeranga P. Rajan, Koichiro Takayama, Masahiro Fujita
   Model Checking Based on Sequential ATPG. [Citation Graph (0, 0)][DBLP]
   CAV, 1999, pp:418-430 [Conf]
   
3. Shuo Sheng, Koichiro Takayama, Michael S. Hsiao
   Effective safety property checking using simulation-based sequential ATPG. [Citation Graph (0, 0)][DBLP]
   DAC, 2002, pp:813-818 [Conf]
   
4. Rajarshi Mukherjee, Jawahar Jain, Koichiro Takayama, Masahiro Fujita, Jacob A. Abraham, Donald S. Fussell
   An Efficient Filter-Based Approach for Combinational Verification. [Citation Graph (0, 0)][DBLP]
   DATE, 1999, pp:132-137 [Conf]
   
5. Farzan Fallah, Koichiro Takayama
   A New Functional Test Program Generation Methodology. [Citation Graph (0, 0)][DBLP]
   ICCD, 2001, pp:76-81 [Conf]
   
6. Fumiyasu Hirose, Koichiro Takayama, Nobuaki Kawato
   A Method to Generate Tests for Combinational Logic Circuits Using an Ultra-High-Speed Logic Simulator. [Citation Graph (0, 0)][DBLP]
   ITC, 1988, pp:102-107 [Conf]
   
7. Rajarshi Mukherjee, Jawahar Jain, Koichiro Takayama, Jacob A. Abraham, Donald S. Fussell, Masahiro Fujita
   Efficient Combinational Verification Using Overlapping Local BDDs and a Hash Table. [Citation Graph (0, 0)][DBLP]
   Formal Methods in System Design, 2002, v:21, n:1, pp:95-101 [Journal]
   
8. Rajarshi Mukherjee, Jawahar Jain, Koichiro Takayama, Masahiro Fujita, Jacob A. Abraham, Donald S. Fussell
   An efficient filter-based approach for combinational verification. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:11, pp:1542-1557 [Journal]
   
9. Subramanian Rajagopalan, Sreeranga P. Rajan, Sharad Malik, Sandro Rigo, Guido Araujo, Koichiro Takayama
   A retargetable VLIW compiler framework for DSPs withinstruction-level parallelism. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:11, pp:1319-1328 [Journal]