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Ramachandra Achar: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Natalie Nakhla, Ramachandra Achar, Michel S. Nakhla, Anestis Dounavis
    Delay extraction based closed-form SPICE compatible passive macromodels for distributed transmission line interconnects. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:1082-1085 [Conf]
  2. Emad Gad, Anestis Dounavis, Michel S. Nakhla, Ramachandra Achar
    Passive model order reduction of multiport distributed interconnects. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:526-531 [Conf]
  3. Ramachandra Achar, Michel S. Nakhla, Qi-Jun Zhang
    Addressing high frequency effects in VLSI interconnects with full wave model and CFH. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:53-56 [Conf]
  4. Guowu Zheng, Qi-Jun Zhang, Michel S. Nakhla, Ramachandra Achar
    An efficient approach for moment-matching simulation of linear subnetworks with measured or tabulated data. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1996, pp:20-23 [Conf]
  5. Natalie Nakhla, Ramachandra Achar, Michel S. Nakhla
    Accurate and closed-form SPICE compatible passive macromodels for distributed interconnects with frequency dependent parameters. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5770-5773 [Conf]
  6. Natalie Nakhla, Anestis Dounavis, Ramachandra Achar, Michel S. Nakhla
    Fast sensitivity analysis of transmission line networks. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2004, pp:121-124 [Conf]
  7. Praveen Pai, Emad Gad, Ramachandra Achar, Roni Khazaka, Michel S. Nakhla
    Computing large-change sensitivity of periodic responses of nonlinear circuits using reduction techniques. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2004, pp:333-336 [Conf]
  8. Dharmendra Saraswat, Ramachandra Achar, Michel S. Nakhla
    Passive macromodeling of subnetworks characterized by measured data. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2003, pp:502-505 [Conf]
  9. Ramachandra Achar, Michel S. Nakhla
    Efficient simulation of on-chip RF components using model-reduction techniques. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 1999, pp:81-84 [Conf]
  10. Pavan K. Gunupudi, Michel S. Nakhla, Ramachandra Achar
    Multi-point multi-port reduction of high-speed distributed interconnects using Krylov-space techniques. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 1999, pp:242-245 [Conf]
  11. Dharmendra Saraswat, Ramachandra Achar, Michel S. Nakhla
    Projection Based Fast Passive Compact Macromodeling of High-Speed VLSI Circuits and Interconnects. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:629-633 [Conf]
  12. Dharmendra Saraswat, Ramachandra Achar, Michel S. Nakhla
    Circuit Compatible Macromodeling of High-Speed VLSI Modules Characterized by Scattering Parameters. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:667-671 [Conf]
  13. Gurpreet Shinh, Natalie Nakhla, Ramachandra Achar, Michel S. Nakhla, Ihsan Erdin
    Efficient and Accurate EMC Analysis of High-Frequency VLSI Subnetworks. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:672-676 [Conf]
  14. Ramachandra Achar, Michel S. Nakhla, Qi-Jun Zhang
    Full-wave analysis of high-speed interconnects using complex frequency hopping. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:10, pp:997-1016 [Journal]
  15. Pavan K. Gunupudi, Michel S. Nakhla, Ramachandra Achar
    Simulation of high-speed distributed interconnects usingKrylov-space techniques. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:7, pp:799-808 [Journal]
  16. Dharmendra Saraswat, Ramachandra Achar, Michel S. Nakhla
    Global Passivity Enforcement Algorithm for Macromodels of Interconnect Subnetworks Characterized by Tabulated Data. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:7, pp:819-832 [Journal]
  17. Dharmendra Saraswat, Ramachandra Achar, Michel S. Nakhla
    Fast Passivity Verification and Enforcement via Reciprocal Systems for Interconnects With Large Order Macromodels. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:1, pp:48-59 [Journal]

  18. Sparse and passive reduction of massively coupled large multiport interconnects. [Citation Graph (, )][DBLP]


  19. On passivity enforcement for macromodels of S-parameter based tabulated subnetworks. [Citation Graph (, )][DBLP]


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