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Simon W. Moore: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Kate Taylor, Simon Moore
    My Compiler Really Understands Me: An Adaptive Programming Language Tutor. [Citation Graph (0, 0)][DBLP]
    AH, 2006, pp:389-392 [Conf]
  2. Robert D. Mullins, Andrew West, Simon W. Moore
    The design and implementation of a low-latency on-chip network. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:164-169 [Conf]
  3. Scott Fairbanks, Simon W. Moore
    Analog Micropipeline Rings for High Precision Timing. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2004, pp:41-50 [Conf]
  4. Scott Fairbanks, Simon W. Moore
    Self-Timed Circuitry for Global Clocking. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2005, pp:86-96 [Conf]
  5. George S. Taylor, Simon W. Moore, Robert D. Mullins, Peter Robinson
    Point to Point GALS Interconnect. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2002, pp:69-75 [Conf]
  6. George S. Taylor, Simon W. Moore, Steve Wilcox, Peter Robinson
    An On-Chip Dynamically Recalibrated Delay Line for Embedded Self-Timed Systems. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2000, pp:45-51 [Conf]
  7. Simon W. Moore, Robert D. Mullins, Paul A. Cunningham, Ross J. Anderson, George S. Taylor
    Improving Smart Card Security Using Self-Timed Circuits. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2002, pp:211-0 [Conf]
  8. Robert D. Mullins, Simon W. Moore
    Demystifying Data-Driven and Pausible Clocking Schemes. [Citation Graph (0, 0)][DBLP]
    ASYNC, 2007, pp:175-185 [Conf]
  9. Petros Oikonomakos, Jacques J. A. Fournier, Simon W. Moore
    Implementing Cryptography on TFT Technology for Secure Display Applications. [Citation Graph (0, 0)][DBLP]
    CARDIS, 2006, pp:32-47 [Conf]
  10. Huiyun Li, A. Theodore Markettos, Simon W. Moore
    Security Evaluation Against Electromagnetic Analysis at Design Time. [Citation Graph (0, 0)][DBLP]
    CHES, 2005, pp:280-292 [Conf]
  11. Jacques J. A. Fournier, Simon W. Moore, Huiyun Li, Robert D. Mullins, George S. Taylor
    Security Evaluation of Asynchronous Circuits. [Citation Graph (0, 0)][DBLP]
    CHES, 2003, pp:137-151 [Conf]
  12. Jacques J. A. Fournier, Simon W. Moore
    A Vector Approach to Cryptography Implementation. [Citation Graph (0, 0)][DBLP]
    DRMTICS, 2005, pp:277-297 [Conf]
  13. Petros Oikonomakos, Simon W. Moore
    An Asynchronous PLA with Improved Security Characteristics. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:257-264 [Conf]
  14. Jacques J. A. Fournier, Simon W. Moore
    Hardware-Software Codesign of a Vector Co-processor for Public Key Cryptography. [Citation Graph (0, 0)][DBLP]
    DSD, 2006, pp:439-446 [Conf]
  15. Simon W. Moore
    Protecting Consumer Security Devices. [Citation Graph (0, 0)][DBLP]
    E-smart, 2001, pp:1- [Conf]
  16. Simon W. Moore, George S. Taylor, Paul A. Cunningham, Robert D. Mullins, Peter Robinson
    Self-Calibrating Clocks for Globally Asynchronous Locally Synchronous Systems. [Citation Graph (0, 0)][DBLP]
    ICCD, 2000, pp:73-0 [Conf]
  17. Panit Watcharawitch, Simon W. Moore
    JMA: The Java-Multithreading Architecture for Embedded Processors. [Citation Graph (0, 0)][DBLP]
    ICCD, 2002, pp:527-0 [Conf]
  18. Robert D. Mullins, Andrew West, Simon W. Moore
    Low-Latency Virtual-Channel Routers for On-Chip Networks. [Citation Graph (0, 0)][DBLP]
    ISCA, 2004, pp:188-197 [Conf]
  19. Simon Hollis, Simon W. Moore
    An Asynchronous Interconnect Architecture for Device Security Enhancement. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:209-215 [Conf]
  20. Simon W. Moore, Brian T. Graham
    Tagged Up/Down Sorter - A Hardware Priority Queue. [Citation Graph (0, 0)][DBLP]
    Comput. J., 1995, v:38, n:9, pp:695-703 [Journal]
  21. Simon W. Moore, Ross J. Anderson, Robert D. Mullins, George S. Taylor, Jacques J. A. Fournier
    Balanced self-checking asynchronous logic for smart card applications. [Citation Graph (0, 0)][DBLP]
    Microprocessors and Microsystems, 2003, v:27, n:9, pp:421-430 [Journal]
  22. Simon Hollis, Simon W. Moore
    An area-efficient, pulse-based interconnect. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  23. Arnab Banerjee, Robert Mullins, Simon Moore
    A Power and Energy Exploration of Network-on-Chip Architectures. [Citation Graph (0, 0)][DBLP]
    NOCS, 2007, pp:163-172 [Conf]
  24. Daniel Greenfield, Arnab Banerjee, Jeong-Gun Lee, Simon Moore
    Implications of Rent's Rule for NoC Design and Its Fault-Tolerance. [Citation Graph (0, 0)][DBLP]
    NOCS, 2007, pp:283-294 [Conf]

  25. The Frequency Injection Attack on Ring-Oscillator-Based True Random Number Generators. [Citation Graph (, )][DBLP]

  26. FPGAs with time-division multiplexed wiring: an architectural exploration and area analysis. [Citation Graph (, )][DBLP]

  27. RasP: An Area-efficient, On-chip Network. [Citation Graph (, )][DBLP]

  28. The next resource war: computation vs. communication. [Citation Graph (, )][DBLP]

  29. Fractal communication in software data dependency graphs. [Citation Graph (, )][DBLP]

  30. Flow-aware allocation for on-chip networks. [Citation Graph (, )][DBLP]

  31. A Network of Time-Division Multiplexed Wiring for FPGAs. [Citation Graph (, )][DBLP]

  32. Implications of Electronics Technology Trends to Algorithm Design. [Citation Graph (, )][DBLP]

  33. Implications of Electronics Technology Trends for Algorithm Design. [Citation Graph (, )][DBLP]

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