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Mohammad M. Mansour: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Makram M. Mansour, Mohammad M. Mansour, Amit Mehrotra
    Analysis of MOS cross-coupled LC-tank oscillators using short-channel device equations. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:181-185 [Conf]
  2. M. M. Mansour, Amit Mehrotra
    Efficient core designs based on parameterized macrocells with accurate delay models. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:517-520 [Conf]
  3. Mohammad M. Mansour, Naresh R. Shanbhag
    Architecture-aware low-density parity-check codes. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2003, pp:57-60 [Conf]
  4. Mohammad M. Mansour, Naresh R. Shanbhag
    Simplified current and delay models for deep submicron CMOS digital circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:109-112 [Conf]
  5. Mohammad M. Mansour, Naresh R. Shanbhag
    Low-power VLSI decoder architectures for LDPC codes. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2002, pp:284-289 [Conf]
  6. Makram M. Mansour, Mohammad M. Mansour, Amit Mehrotra
    Parameterized Macrocells with Accurate Delay Models for Core-Based Designs. [Citation Graph (0, 0)][DBLP]
    ISQED, 2003, pp:319-0 [Conf]
  7. Makram M. Mansour, Mohammad M. Mansour, Amit Mehrotra
    Modified Sakurai-Newton Current Model and its Applications to CMOS Digital Circuit Design. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:62-69 [Conf]
  8. Mohammad M. Mansour, Naresh R. Shanbhag
    High-throughput LDPC decoders. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:6, pp:976-996 [Journal]
  9. Mohammad M. Mansour, Naresh R. Shanbhag
    VLSI architectures for SISO-APP decoders. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:4, pp:627-650 [Journal]

  10. Optimized Architecture for Computing Zadoff-Chu Sequences with Application to LTE. [Citation Graph (, )][DBLP]


  11. Parallel channel interleavers for 3GPP2/UMB. [Citation Graph (, )][DBLP]


  12. A parallel architecture for 3GPP2/UMB turbo interleavers. [Citation Graph (, )][DBLP]


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