The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

César A. M. Marcon: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. César A. M. Marcon, André Borin Suarez, Altamiro Amadeu Susin, Luigi Carro, Flávio Rech Wagner
    Time and energy efficient mapping of embedded applications onto NoCs. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:33-38 [Conf]
  2. César A. M. Marcon, Ney Laert Vilar Calazans, Fernando Gehm Moraes, Altamiro Amadeu Susin, Igor M. Reis, Fabiano Hessel
    Exploring NoC Mapping Strategies: An Energy and Timing Aware Technique. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:502-507 [Conf]
  3. Márcio Eduardo Kreutz, César A. M. Marcon, Luigi Carro, Altamiro Amadeu Susin, Ney Laert Vilar Calazans
    Energy and latency evaluation of NoC topologies. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5866-5869 [Conf]
  4. Fabiano Hessel, César A. M. Marcon, Tatiana Gadelha Serra Dos Santos
    High Level RTOS Scheduler Modeling for a Fast Design Validation. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:461-466 [Conf]
  5. Fabiano Hessel, Vitor M. da Rosa, Igor M. Reis, Ricardo Planner, César A. M. Marcon, Altamiro Amadeu Susin
    Abstract RTOS Modeling for Embedded Systems. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2004, pp:210-216 [Conf]
  6. César A. M. Marcon, Márcio Eduardo Kreutz, Altamiro Amadeu Susin, Ney Laert Vilar Calazans
    Models for Embedded Application Mapping onto NoCs: Timing Analysis. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2005, pp:17-23 [Conf]
  7. Melissa Vetromille, Luciano Ost, César A. M. Marcon, Carlos Eduardo Reif, Fabiano Hessel
    RTOS Scheduler Implementation in Hardware and Software for Real Time Applications. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2006, pp:163-168 [Conf]
  8. José Carlos S. Palma, César A. M. Marcon, Fernando Gehm Moraes, Ney Laert Vilar Calazans, Ricardo A. L. Reis, Altamiro Amadeu Susin
    Mapping embedded systems onto NoCs: the traffic effect on dynamic energy estimation. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2005, pp:196-201 [Conf]
  9. Márcio Eduardo Kreutz, César A. M. Marcon, Luigi Carro, Flávio Rech Wagner, Altamiro Amadeu Susin
    Design space exploration comparing homogeneous and heterogeneous network-on-chip architectures. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2005, pp:190-195 [Conf]
  10. Fabiano Hessel, Vitor M. da Rosa, Carlos Eduardo Reif, César A. M. Marcon, Tatiana Gadelha Serra Dos Santos
    Scheduling refinement in abstract RTOS models. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2006, v:5, n:2, pp:342-354 [Journal]
  11. César A. M. Marcon, Edson I. Moreno, Ney Laert Vilar Calazans, Fernando Gehm Moraes
    Evaluation of Algorithms for Low Energy Mapping onto NoCs. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:389-392 [Conf]
  12. David Matschulat, César A. M. Marcon, Fabiano Hessel
    ER-EDF: A QoS Scheduler for Real-Time Embedded Systems. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2007, pp:181-188 [Conf]
  13. César A. M. Marcon, José Carlos S. Palma, Ney Laert Vilar Calazans, Fernando Gehm Moraes, Altamiro Amadeu Susin, Ricardo Augusto da Luz Reis
    Modeling the Traffic Effect for the Application Cores Mapping Problem onto NoCs. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2005, pp:179-194 [Conf]
  14. César A. M. Marcon, Ney Laert Vilar Calazans, Fernando Gehm Moraes, Altamiro Amadeu Susin, Igor M. Reis, Fabiano Hessel
    Exploring NoC Mapping Strategies: An Energy and Timing Aware Technique [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]

  15. A Passive 915 MHz UHF RFID Tag. [Citation Graph (, )][DBLP]


  16. A QoS Scheduler for Real-Time Embedded Systems. [Citation Graph (, )][DBLP]


  17. A 915 MHz UHF low power RFID tag. [Citation Graph (, )][DBLP]


  18. A VHDL based approach for fast and accurate energy consumption estimations. [Citation Graph (, )][DBLP]


  19. A Flexible Design Flow for a Low Power RFID Tag. [Citation Graph (, )][DBLP]


Search in 0.002secs, Finished in 0.003secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002