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Altamiro Amadeu Susin: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. César A. M. Marcon, André Borin Suarez, Altamiro Amadeu Susin, Luigi Carro, Flávio Rech Wagner
    Time and energy efficient mapping of embedded applications onto NoCs. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:33-38 [Conf]
  2. Carla Lopes, Erik Schüler, Paulo Engel, Altamiro Amadeu Susin
    ERP signal identification of Individuals at Risk for Alcoholism using Learning Vector Quantization Network. [Citation Graph (0, 0)][DBLP]
    CIBCB, 2005, pp:283-287 [Conf]
  3. Marcelo Negreiros, Luigi Carro, Altamiro Amadeu Susin
    Ultimate low cost analog BIST. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:570-573 [Conf]
  4. César A. M. Marcon, Ney Laert Vilar Calazans, Fernando Gehm Moraes, Altamiro Amadeu Susin, Igor M. Reis, Fabiano Hessel
    Exploring NoC Mapping Strategies: An Energy and Timing Aware Technique. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:502-507 [Conf]
  5. Marcelo Negreiros, Luigi Carro, Altamiro Amadeu Susin
    Low Cost Analog Testing of RF Signal Paths. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:292-297 [Conf]
  6. Marcelo Negreiros, Luigi Carro, Altamiro Amadeu Susin
    Noise Figure Evaluation Using Low Cost BIST. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:158-163 [Conf]
  7. Marcelo Negreiros, Luigi Carro, Altamiro Amadeu Susin
    An improved RF loopback for test time reduction. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:646-651 [Conf]
  8. Cesar Albenes Zeferino, Márcio Eduardo Kreutz, Altamiro Amadeu Susin
    RASoC: A Router Soft-Core for Networks-on-Chip. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:198-205 [Conf]
  9. Alex Ngouanga, Gilles Sassatelli, Lionel Torres, André Soares, Altamiro Amadeu Susin
    A Contextual Resources use: a Proof of Concept through the APACHES' Platform. [Citation Graph (0, 0)][DBLP]
    DDECS, 2006, pp:44-49 [Conf]
  10. Luigi Carro, G. A. Pereira, C. Alba, Altamiro Amadeu Susin
    System Design using ASIPs. [Citation Graph (0, 0)][DBLP]
    ECBS, 1996, pp:80-85 [Conf]
  11. Luigi Carro, Altamiro Amadeu Susin
    A Risc Architecture to Explore HW/SW Parallelism in HW/SW Co-Design. [Citation Graph (0, 0)][DBLP]
    ECBS, 1996, pp:382-388 [Conf]
  12. C. Alba, Luigi Carro, A. Lima, Altamiro Amadeu Susin
    Embedded Systems Design with Frontend Compilers. [Citation Graph (0, 0)][DBLP]
    ICCD, 1996, pp:200-0 [Conf]
  13. Leticia V. Guimaraes, André Soares, Viviane Cordeiro, Altamiro Amadeu Susin
    Gradient Pile up Algorithm for Edge Enhancement and Detection. [Citation Graph (0, 0)][DBLP]
    ICIAR (1), 2004, pp:187-194 [Conf]
  14. Marcelo Negreiros, Luigi Carro, Altamiro Amadeu Susin
    A Statistical Sampler for a New On-line Analog Test Method. [Citation Graph (0, 0)][DBLP]
    IOLTW, 2002, pp:79-0 [Conf]
  15. Marcelo Negreiros, Luigi Carro, Altamiro Amadeu Susin
    Low Cost On-Line Testing of RF Circuits. [Citation Graph (0, 0)][DBLP]
    IOLTS, 2004, pp:73-78 [Conf]
  16. A. B. Soares, Luigi Carro, Altamiro Amadeu Susin
    Reconfigurable communications for image processing applications. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2006, pp:- [Conf]
  17. Rodrigo Ferrugem Cardoso, Márcio Eduardo Kreutz, Luigi Carro, Altamiro Amadeu Susin
    Design space exploration on heterogeneous network-on-chip. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:428-431 [Conf]
  18. Leticia V. Guimaraes, André Soares, Viviane Cordeiro, Altamiro Amadeu Susin
    Gradient pile up for edge detection on hardware. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5834-5837 [Conf]
  19. Márcio Eduardo Kreutz, César A. M. Marcon, Luigi Carro, Altamiro Amadeu Susin, Ney Laert Vilar Calazans
    Energy and latency evaluation of NoC topologies. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5866-5869 [Conf]
  20. Josias O. Mainardi, Adão Antônio de Souza Jr., Luigi Carro, Altamiro Amadeu Susin
    A comparison of totally digital ADCs for SOCs. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2004, pp:641-644 [Conf]
  21. Luciano Severino de Paula, Eric E. Fabris, Sergio Bampi, Altamiro Amadeu Susin
    A High Swing Low Power CMOS Differential Voltage-Controlled Ring Oscillator. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:467-470 [Conf]
  22. Bruno Zatt, Arnaldo Azevedo, Luciano Volcan Agostini, Altamiro Amadeu Susin, Sergio Bampi
    Memory Hierarchy Targeting Bi-Predictive Motion Compensation for H.264/AVC Decoder. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:445-446 [Conf]
  23. Fabiano Hessel, Vitor M. da Rosa, Igor M. Reis, Ricardo Planner, César A. M. Marcon, Altamiro Amadeu Susin
    Abstract RTOS Modeling for Embedded Systems. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2004, pp:210-216 [Conf]
  24. César A. M. Marcon, Márcio Eduardo Kreutz, Altamiro Amadeu Susin, Ney Laert Vilar Calazans
    Models for Embedded Application Mapping onto NoCs: Timing Analysis. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2005, pp:17-23 [Conf]
  25. José Carlos S. Palma, César A. M. Marcon, Fernando Gehm Moraes, Ney Laert Vilar Calazans, Ricardo A. L. Reis, Altamiro Amadeu Susin
    Mapping embedded systems onto NoCs: the traffic effect on dynamic energy estimation. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2005, pp:196-201 [Conf]
  26. Cesar Albenes Zeferino, Frederico G. M. E. Santo, Altamiro Amadeu Susin
    ParIS: a parameterizable interconnect switch for networks-on-chip. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2004, pp:204-209 [Conf]
  27. Márcio Eduardo Kreutz, César A. M. Marcon, Luigi Carro, Flávio Rech Wagner, Altamiro Amadeu Susin
    Design space exploration comparing homogeneous and heterogeneous network-on-chip architectures. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2005, pp:190-195 [Conf]
  28. Marcelo Negreiros, Erik Schüler, Luigi Carro, Altamiro Amadeu Susin
    Testing RF Signal Paths Using Spectral Analysis and Subsampling. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2003, pp:329-0 [Conf]
  29. Cesar Albenes Zeferino, Altamiro Amadeu Susin
    SoCIN: A Parametric and Scalable Network-on-Chip. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2003, pp:169-0 [Conf]
  30. Érika F. Cota, Márcio Eduardo Kreutz, Cesar Albenes Zeferino, Luigi Carro, Marcelo Lubaszewski, Altamiro Amadeu Susin
    The Impact of NoC Reuse on the Testing of Core-based Systems. [Citation Graph (0, 0)][DBLP]
    VTS, 2003, pp:128-133 [Conf]
  31. Marcelo Negreiros, Luigi Carro, Altamiro Amadeu Susin
    Ultra Low Cost Analog BIST Using Spectral Analysis. [Citation Graph (0, 0)][DBLP]
    VTS, 2003, pp:77-82 [Conf]
  32. Marcelo Negreiros, Adão Antônio de Souza Jr., Luigi Carro, Altamiro Amadeu Susin
    RF Digital Signal Generation Beyond Nyquist. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:15-22 [Conf]
  33. Márcio Eduardo Kreutz, Cesar Albenes Zeferino, Luigi Carro, Altamiro Amadeu Susin
    Análise e Seleção de Redes de Interconexão para Síntese de Sistemas no Ambiente S3E2S. [Citation Graph (0, 0)][DBLP]
    RITA, 2001, v:8, n:1, pp:83-101 [Journal]
  34. Luciano Volcan Agostini, Arnaldo Azevedo, Vagner S. Rosa, Eduardo A. Berriel, Tatiana G. S. dos Santos, Sergio Bampi, Altamiro Amadeu Susin
    FPGA Design of A H.264/AVC Main Profile Decoder for HDTV. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-6 [Conf]
  35. A. B. Soares, Altamiro Amadeu Susin, Leticia V. Guimaraes
    Automatic generation of neural networks for image processing. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  36. Vagner S. Rosa, Wagston T. Staehler, Arnaldo Azevedo, Bruno Zatt, Roger E. Porto, Luciano Volcan Agostini, Sergio Bampi, Altamiro Amadeu Susin
    FPGA Prototyping Strategy for a H.264/AVC Video Decoder. [Citation Graph (0, 0)][DBLP]
    IEEE International Workshop on Rapid System Prototyping, 2007, pp:174-180 [Conf]
  37. Wagston T. Staehler, Eduardo A. Berriel, Altamiro Amadeu Susin, Sergio Bampi
    Architecture of an HDTV Intraframe Predictor for a H.264 Decoder. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:228-233 [Conf]
  38. César A. M. Marcon, José Carlos S. Palma, Ney Laert Vilar Calazans, Fernando Gehm Moraes, Altamiro Amadeu Susin, Ricardo Augusto da Luz Reis
    Modeling the Traffic Effect for the Application Cores Mapping Problem onto NoCs. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2005, pp:179-194 [Conf]
  39. Alex Ngouanga, Gilles Sassatelli, Lionel Torres, Thierry Gil, André Borin Suarez, Altamiro Amadeu Susin
    Run-Time Resources Management on Coarse Grained, Packet-Switching Reconfigurable Architecture: A Case Study Through the APACHES' Platform. [Citation Graph (0, 0)][DBLP]
    ARC, 2006, pp:134-145 [Conf]
  40. Marcelo Negreiros, Luigi Carro, Altamiro Amadeu Susin
    Digital Generation of Signals for Low Cost RF BIST. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2007, pp:49-54 [Conf]
  41. Marcelo Negreiros, Luigi Carro, Altamiro Amadeu Susin
    Noise Figure Evaluation Using Low Cost BIST [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  42. César A. M. Marcon, Ney Laert Vilar Calazans, Fernando Gehm Moraes, Altamiro Amadeu Susin, Igor M. Reis, Fabiano Hessel
    Exploring NoC Mapping Strategies: An Energy and Timing Aware Technique [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  43. Marcelo Negreiros, Luigi Carro, Altamiro Amadeu Susin
    Testing analog circuits using spectral analysis. [Citation Graph (0, 0)][DBLP]
    Microelectronics Journal, 2003, v:34, n:10, pp:937-944 [Journal]
  44. Maria Da Gloria Flores, Marcelo Negreiros, Luigi Carro, Altamiro Amadeu Susin, Felipe R. Clayton, Cristiano Benevento
    Low Cost BIST for Static and Dynamic Testing of ADCs. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2005, v:21, n:3, pp:283-290 [Journal]
  45. Marcelo Negreiros, Luigi Carro, Altamiro Amadeu Susin
    Low Cost On-Line Testing Strategy for RF Circuits. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2005, v:21, n:4, pp:417-427 [Journal]

  46. A high throughput and low cost diamond search architecture for HDTV motion estimation. [Citation Graph (, )][DBLP]


  47. A real time H.264/AVC intra frame prediction hardware architecture for HDTV 1080P video. [Citation Graph (, )][DBLP]


  48. HP422-MoCHA: A H.264/AVC High Profile motion compensation architecture for HDTV. [Citation Graph (, )][DBLP]


  49. Proposal of an improved motion estimation module for SVC. [Citation Graph (, )][DBLP]


  50. A wide band CMOS differential voltage-controlled ring oscillator. [Citation Graph (, )][DBLP]


  51. A new march sequence to fit DDR SDRAM test in burst mode. [Citation Graph (, )][DBLP]


  52. Architectural design for the new QSDS with dynamic iteration control motion estimation algorithm targeting HDTV. [Citation Graph (, )][DBLP]


  53. A new pipelined architecture of an H.264/MPEG-4 AVC deblocking filter. [Citation Graph (, )][DBLP]


  54. High throughput architecture for H.264/AVC motion compensation sample interpolator for HDTV. [Citation Graph (, )][DBLP]


  55. High performance and low cost architecture for H.264/AVC CAVLD targeting HDTV. [Citation Graph (, )][DBLP]


  56. Fault tolerant mechanism to improve yield in NoCs using a reconfigurable router. [Citation Graph (, )][DBLP]


  57. An HDTV H.264 deblocking filter in FPGA with RGB video output. [Citation Graph (, )][DBLP]


  58. A Pipelined 8x8 2-D Forward DCT Hardware Architecture for H.264/AVC High Profile Encoder. [Citation Graph (, )][DBLP]


  59. Motion Compensation Hardware Accelerator Architecture for H.264/AVC. [Citation Graph (, )][DBLP]


  60. High Throughput Hardware Architecture for Motion Estimation with 4: 1 Pel Subsampling Targeting Digital Television Applications. [Citation Graph (, )][DBLP]


  61. A High Performance H.264 Deblocking Filter. [Citation Graph (, )][DBLP]


  62. The Need for Reconfigurable Routers in Networks-on-Chip. [Citation Graph (, )][DBLP]


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