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Luca Benini: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Srinivasan Murali, Luca Benini, Giovanni De Micheli
    Mapping and physical planning of networks-on-chip architectures with quality-of-service guarantees. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:27-32 [Conf]
  2. Daniele Masotti, Elisa Ficarra, Enrico Macii, Luca Benini
    Techniques for Enhancing Computation of DNA Curvature Molecules. [Citation Graph (0, 0)][DBLP]
    BIBE, 2004, pp:22-29 [Conf]
  3. Sungroh Yoon, Christine Nardini, Luca Benini, Giovanni De Micheli
    Enhanced pClustering and Its Applications to Gene Expression Data. [Citation Graph (0, 0)][DBLP]
    BIBE, 2004, pp:275-282 [Conf]
  4. Federico Angiolini, Luca Benini, Alberto Caprara
    Polynomial-time algorithm for on-chip scratchpad memory partitioning. [Citation Graph (0, 0)][DBLP]
    CASES, 2003, pp:318-326 [Conf]
  5. Federico Angiolini, Francesco Menichelli, Alberto Ferrero, Luca Benini, Mauro Olivieri
    A post-compiler approach to scratchpad mapping of code. [Citation Graph (0, 0)][DBLP]
    CASES, 2004, pp:259-267 [Conf]
  6. Davide Bruni, Luca Benini, Bruno Riccò
    System lifetime extension by battery management: an experimental work. [Citation Graph (0, 0)][DBLP]
    CASES, 2002, pp:232-237 [Conf]
  7. Franco Gatti, Andrea Acquaviva, Luca Benini, Bruno Riccò
    Low Power Control Techniques For TFT LCD Displays. [Citation Graph (0, 0)][DBLP]
    CASES, 2002, pp:218-224 [Conf]
  8. Elisa Ficarra, Enrico Macii, Giovanni De Micheli, Luca Benini
    Computer-Aided Evaluation of Protein Expression in Pathological Tissue Images. [Citation Graph (0, 0)][DBLP]
    CBMS, 2006, pp:413-418 [Conf]
  9. Iyad Al Khatib, Davide Bertozzi, Francesco Poletti, Luca Benini, Axel Jantsch, Mohamed Bechara, Hasan Khalifeh, Mazen Hajjar, Rustam Nabiev, Sven Jonsson
    MPSoC ECG biochip: a multiprocessor system-on-chip for real-time human heart monitoring and analysis. [Citation Graph (0, 0)][DBLP]
    Conf. Computing Frontiers, 2006, pp:21-28 [Conf]
  10. Andrea Acquaviva, Luca Benini, Bruno Riccò
    Processor frequency setting for energy minimization of streaming multimedia application. [Citation Graph (0, 0)][DBLP]
    CODES, 2001, pp:249-253 [Conf]
  11. Yung-Hsiang Lu, Luca Benini, Giovanni De Micheli
    Low-power task scheduling for multiple devices. [Citation Graph (0, 0)][DBLP]
    CODES, 2000, pp:39-43 [Conf]
  12. Luca Benini, Davide Bertozzi, Alessio Guerri, Michela Milano
    Allocation and Scheduling for MPSoCs via Decomposition and No-Good Generation. [Citation Graph (0, 0)][DBLP]
    CP, 2005, pp:107-121 [Conf]
  13. Luca Benini, Davide Bertozzi, Alessio Guerri, Michela Milano
    Allocation, Scheduling and Voltage Scaling on Energy Aware MPSoCs. [Citation Graph (0, 0)][DBLP]
    CPAIOR, 2006, pp:44-58 [Conf]
  14. David Atienza, Pablo Garcia Del Valle, Giacomo Paci, Francesco Poletti, Luca Benini, Giovanni De Micheli, Jose Manuel Mendias
    A fast HW/SW FPGA-based thermal emulation framework for multi-processor system-on-chip. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:618-623 [Conf]
  15. Luca Benini, Giovanni De Micheli, Antonio Lioy, Enrico Macii, Giuseppe Odasso, Massimo Poncino
    Computational Kernels and their Application to Sequential Power Optimization. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:764-769 [Conf]
  16. Luca Benini, Luca Macchiarulo, Alberto Macii, Enrico Macii, Massimo Poncino
    From Architecture to Layout: Partitioned Memory Synthesis for Embedded Systems-on-Chip. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:784-789 [Conf]
  17. Luca Benini, Giovanni De Micheli, Enrico Macii, Giuseppe Odasso, Massimo Poncino
    Kernel-Based Power Optimization of RTL Components: Exact and Approximate Extraction Algorithms. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:247-252 [Conf]
  18. Luca Benini, Alberto Macii, Enrico Macii, Elvira Omerbegovic, Fabrizio Pro, Massimo Poncino
    Energy-aware design techniques for differential power analysis protection. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:36-41 [Conf]
  19. Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino
    Synthesis of application-specific memories for power optimization in embedded systems. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:300-303 [Conf]
  20. Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino, Riccardo Scarsi
    Synthesis of Low-Overhead Interfaces for Power-Efficient Communication over Wide Buses. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:128-133 [Conf]
  21. Luca Benini, Enrico Macii, Massimo Poncino
    Telescopic Units: Increasing the Average Throughput of Pipelined Designs by Adaptive Latency Control. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:22-27 [Conf]
  22. Alessandro Bogliolo, Luca Benini, Bruno Riccò
    Power Estimation of Cell-Based CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:433-438 [Conf]
  23. Davide Bruni, Alessandro Bogliolo, Luca Benini
    Statistical Design Space Exploration for Application-Specific Unit Synthesis. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:641-646 [Conf]
  24. Marcello Dalpasso, Alessandro Bogliolo, Luca Benini
    Hardware/software IP protection. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:593-596 [Conf]
  25. Marcello Dalpasso, Alessandro Bogliolo, Luca Benini
    Virtual Simulation of Distributed IP-based Designs. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:50-55 [Conf]
  26. Monica Donno, Alessandro Ivaldi, Luca Benini, Enrico Macii
    Clock-tree power optimization based on RTL clock-gating. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:622-627 [Conf]
  27. Francesco Poletti, Paul Marchal, David Atienza, Luca Benini, Francky Catthoor, Jose Manuel Mendias
    An integrated hardware/software approach for run-time scratchpad management. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:238-243 [Conf]
  28. Iyad Al Khatib, Francesco Poletti, Davide Bertozzi, Luca Benini, Mohamed Bechara, Hasan Khalifeh, Axel Jantsch, Rustam Nabiev
    A multiprocessor system-on-chip for real-time biomedical monitoring and analysis: architectural design space exploration. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:125-130 [Conf]
  29. Balakrishna Kumthekar, Luca Benini, Enrico Macii, Fabio Somenzi
    In-Place Power Optimization for LUT-Based FPGAs. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:718-721 [Conf]
  30. Srinivasan Murali, David Atienza, Luca Benini, Giovanni De Micheli
    A multi-path routing strategy with guaranteed in-order packet delivery and fault-tolerance for networks on chip. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:845-848 [Conf]
  31. Giuseppe A. Paleologo, Luca Benini, Alessandro Bogliolo, Giovanni De Micheli
    Policy Optimization for Dynamic Power Management. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:182-187 [Conf]
  32. Tajana Simunic, Luca Benini, Andrea Acquaviva, Peter W. Glynn, Giovanni De Micheli
    Dynamic Voltage Scaling and Power Management for Portable Systems. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:524-529 [Conf]
  33. Tajana Simunic, Luca Benini, Giovanni De Micheli
    Cycle-Accurate Simulation of Energy Consumption in Embedded Systems. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:867-872 [Conf]
  34. Terry Tao Ye, Giovanni De Micheli, Luca Benini
    Analysis of power consumption on switch fabrics in network routers. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:524-529 [Conf]
  35. Luca Benini, Ulrich Kremer, Christian W. Probst, Peter Schelkens
    05141 Summary - Power-aware Computing Systems. [Citation Graph (0, 0)][DBLP]
    Power-aware Computing Systems, 2005, pp:- [Conf]
  36. Luca Benini, Ulrich Kremer, Christian W. Probst, Peter Schelkens
    05141 Abstracts Collection - Power-aware Computing Systems. [Citation Graph (0, 0)][DBLP]
    Power-aware Computing Systems, 2005, pp:- [Conf]
  37. Luca Benini
    Application specific NoC design. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:491-495 [Conf]
  38. Luca Benini, Davide Bruni, Alberto Macii, Enrico Macii
    Hardware-Assisted Data Compression for Energy Minimization in Systems with Embedded Processors. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:449-450 [Conf]
  39. Luca Benini, Giuliano Castelli, Alberto Macii, Enrico Macii, Massimo Poncino, Riccardo Scarsi
    A Discrete-Time Battery Model for High-Level Power Estimation. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:35-0 [Conf]
  40. Pietro Babighian, Luca Benini, Enrico Macii
    A Scalable ODC-Based Algorithm for RTL Insertion of Gated Clocks. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:500-505 [Conf]
  41. Andrea Acquaviva, Luca Benini, Bruno Riccò
    An adaptive algorithm for low-power streaming multimedia processing. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:273-279 [Conf]
  42. Pietro Babighian, Luca Benini, Enrico Macii
    Sizing and Characterization of Leakage-Control Cells for Layout-Aware Distributed Power-Gating. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:720-723 [Conf]
  43. Pietro Babighian, Luca Benini, Alberto Macii, Enrico Macii
    Enabling fine-grain leakage management by voltage anchor insertion. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:868-873 [Conf]
  44. Federico Angiolini, Jianjiang Ceng, Rainer Leupers, Federico Ferrari, Cesare Ferri, Luca Benini
    An integrated open framework for heterogeneous MPSoC design space exploration. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1145-1150 [Conf]
  45. Federico Angiolini, Paolo Meloni, Salvatore Carta, Luca Benini, Luigi Raffo
    Contrasting a NoC and a traditional interconnect fabric with layout awareness. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:124-129 [Conf]
  46. Twan Basten, Luca Benini, Anantha Chandrakasan, Menno Lindwer, Jie Liu, Rex Min, Feng Zhao
    Scaling into Ambient Intelligence. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10076-10083 [Conf]
  47. Luca Benini, Giuliano Castelli, Alberto Macii, Enrico Macii, Massimo Poncino, Riccardo Scarsi
    Extending lifetime of portable systems by battery scheduling. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:197-203 [Conf]
  48. Luca Benini, Alessandro Ivaldi, Alberto Macii, Enrico Macii
    Block-Enabled Memory Macros: Design Space Exploration and Application-Specific Tuning. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:698-699 [Conf]
  49. Luca Benini, Giovanni De Micheli, Alberto Macii, Enrico Macii, Massimo Poncino, Riccardo Scarsi
    Glitch Power Minimization by Gate Freezing. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:163-167 [Conf]
  50. Luca Benini, Giovanni De Micheli, Donatella Sciuto, Enrico Macii, Cristina Silvano
    Address Bus Encoding Techniques for System-Level Power Optimization. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:861-0 [Conf]
  51. Davide Bertozzi, Luca Benini, Giovanni De Micheli
    Low Power Error Resilient Encoding for On-Chip Data Buses. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:102-109 [Conf]
  52. Davide Bertozzi, Anand Raghunathan, Luca Benini, Srivaths Ravi
    Transport Protocol Optimization for Energy Efficient Wireless Embedded Systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10706-10713 [Conf]
  53. Alessandro Bogliolo, Luca Benini, Giovanni De Micheli
    Characterization-Free Behavioral Power Modeling. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:767-773 [Conf]
  54. Marcello Dalpasso, Alessandro Bogliolo, Luca Benini
    Specification and Validation of Distributed IP-Based Designs with JavaCAD. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:684-688 [Conf]
  55. Marcello Dalpasso, Alessandro Bogliolo, Luca Benini, Michele Favalli
    Virtual Fault Simulation of Distributed IP-Based Designs. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:99-0 [Conf]
  56. Eui-Young Chung, Luca Benini, Alessandro Bogliolo, Giovanni De Micheli
    Dynamic Power Management for non-stationary service requests. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:77-81 [Conf]
  57. Antoine Jalabert, Srinivasan Murali, Luca Benini, Giovanni De Micheli
    ×pipesCompiler: A Tool for Instantiating Application Specific Networks on Chip. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:884-889 [Conf]
  58. Simon Künzli, Francesco Poletti, Luca Benini, Lothar Thiele
    Combining simulation and formal methods for system-level performance analysis. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:236-241 [Conf]
  59. Mirko Loghi, Federico Angiolini, Davide Bertozzi, Luca Benini, Roberto Zafalon
    Analyzing On-Chip Communication in a MPSoC Environment. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:752-757 [Conf]
  60. Yung-Hsiang Lu, Eui-Young Chung, Tajana Simunic, Giovanni De Micheli, Luca Benini
    Quantitative Comparison of Power Management Algorithms. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:20-26 [Conf]
  61. Luca Macchiarulo, Luca Benini, Enrico Macii
    On-the-fly layout generation for PTL macrocells. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:546-551 [Conf]
  62. Paul Marchal, José Ignacio Gómez, Luis Piñuel, Davide Bruni, Luca Benini, Francky Catthoor, Henk Corporaal
    SDRAM-Energy-Aware Memory Allocation for Dynamic Multi-Media Applications on Multi-Processor Platforms. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10516-10523 [Conf]
  63. G. Martin, Ralf Seepold, Ting Zhang, Luca Benini, Giovanni De Micheli
    Component selection and matching for IP-based design. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:40-46 [Conf]
  64. Francesco Menichelli, Mauro Olivieri, Luca Benini, Monica Donno, Labros Bisdounis
    A Simulation-Based Power-Aware Architecture Exploration of a Multiprocessor System-on-Chip Design. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:312-317 [Conf]
  65. Giovanni De Micheli, Luca Benini
    Networks on Chip: A New Paradigm for Systems on Chip Design. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:418-419 [Conf]
  66. Giacomo Paci, Paul Marchal, Francesco Poletti, Luca Benini
    Exploring "temperature-aware" design in low-power MPSoCs. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:838-843 [Conf]
  67. Michele Sama, Vincenzo Pacella, Elisabetta Farella, Luca Benini, Bruno Riccò
    3dID: a low-power, low-cost hand motion capture device. [Citation Graph (0, 0)][DBLP]
    DATE Designers' Forum, 2006, pp:136-141 [Conf]
  68. Tajana Simunic, Luca Benini, Peter W. Glynn, Giovanni De Micheli
    Dynamic Power Management of Laptop Hard Disk. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:736- [Conf]
  69. Claudio Stagni, Carlotta Guiducci, Massimo Lanzoni, Luca Benini, Bruno Riccò
    Hardware-Software Design of a Smart Sensor for Fully-Electronic DNA Hybridization Detection. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:198-203 [Conf]
  70. Terry Tao Ye, Luca Benini, Giovanni De Micheli
    Packetized On-Chip Interconnect Communication Analysis for MPSoC. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10344-10349 [Conf]
  71. Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino
    Region Compression: A New Scheme for Memory Energy Minimization in Embedded Systems. [Citation Graph (0, 0)][DBLP]
    EUROMICRO, 1999, pp:1311-1317 [Conf]
  72. Luca Benini, Giovanni De Micheli, Alberto Macii, Enrico Macii, Massimo Poncino
    Reducing Power Consumption of Dedicated Processors Through Instruction Set Encoding. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1998, pp:8-12 [Conf]
  73. Luca Benini, Giovanni De Micheli, Antonio Lioy, Enrico Macii, Giuseppe Odasso, Massimo Poncino
    Timed Supersetting and the Synthesis of Telescopic Units. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1998, pp:331-337 [Conf]
  74. Luca Benini, Alberto Macii, Enrico Macii, Elvira Omerbegovic, Massimo Poncino, Fabrizio Pro
    A novel architecture for power maskable arithmetic units. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2003, pp:136-140 [Conf]
  75. Luca Benini, Giovanni De Micheli, Enrico Macii, Donatella Sciuto, Cristina Silvano
    Asymptotic Zero-Transition Activity Encoding for Address Busses in Low-Power Microprocessor-Based Systems. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1997, pp:77-82 [Conf]
  76. Pietro Babighian, Luca Benini, Alberto Macii, Enrico Macii
    Low-overhead state-retaining elements for low-leakage MTCMOS design. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2005, pp:367-370 [Conf]
  77. Luca Benini, Alessandro Bogliolo, Enrico Macii, Massimo Poncino, Mihai Surmei
    Regression-based RTL power models for controllers. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2000, pp:147-152 [Conf]
  78. Luca Benini, Marco Ferrero, Alberto Macii, Enrico Macii, Massimo Poncino
    Supporting system-level power exploration for DSP applications. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2000, pp:17-22 [Conf]
  79. Mirko Loghi, Martin Letis, Luca Benini, Massimo Poncino
    Exploring the energy efficiency of cache coherence protocols in single-chip multi-processors. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2005, pp:276-281 [Conf]
  80. Mirko Loghi, Massimo Poncino, Luca Benini
    Cycle-accurate power analysis for multiprocessor systems-on-a-chip. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2004, pp:410-406 [Conf]
  81. Kimish Patel, Luca Benini, Enrico Macii, Massimo Poncino
    STV-Cache: a leakage energy-efficient architecture for data caches. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:404-409 [Conf]
  82. Marco Mantovani, Simone Leardini, Martino Ruggiero, Andrea Acquaviva, Luca Benini
    A lightweight parallel java execution environment for embedded multiprocessor systems-on-chip. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:509-512 [Conf]
  83. Andrea Calimera, Antonio Pullini, Ashoka Visweswara Sathanur, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino
    Design of a family of sleep transistor cells for a clustered power-gating flow in 65nm technology. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:501-504 [Conf]
  84. Salvatore Carta, Andrea Acquaviva, Pablo Garcia Del Valle, David Atienza, Giovanni De Micheli, Fernando Rincón, Luca Benini, Jose Manuel Mendias
    Multi-processor operating system emulation framework with thermal feedback for systems-on-chip. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:311-316 [Conf]
  85. Alessandro Bogliolo, Luca Benini
    Node sampling: a robust RTL power modeling approach. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:461-467 [Conf]
  86. Luca Benini, Alessandro Bogliolo, Giovanni De Micheli
    Dynamic power management of electronic systems. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:696-702 [Conf]
  87. Luca Benini, Giovanni De Micheli, Enrico Macii, Massimo Poncino, Riccardo Scarsi
    Fast power estimation for deterministic input streams. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:494-501 [Conf]
  88. Eui-Young Chung, Luca Benini, Giovanni De Micheli
    Dynamic power management using adaptive learning tree. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:274-279 [Conf]
  89. Kimish Patel, Enrico Macii, Luca Benini, Massimo Poncino
    Reducing cache misses by application-specific re-configurable indexing. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:125-130 [Conf]
  90. Patrick Vuillod, Luca Benini, Giovanni De Micheli
    Generalized matching from theory to application. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:13-20 [Conf]
  91. Srinivasan Murali, Paolo Meloni, Federico Angiolini, David Atienza, Salvatore Carta, Luca Benini, Giovanni De Micheli, Luigi Raffo
    Designing application-specific networks on chips with floorplan information. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:355-362 [Conf]
  92. Luca Benini, Davide Bertozzi, Davide Bruni, Nicola Drago, Franco Fummi, Massimo Poncino
    Legacy SystemC Co-Simulation of Multi-Processor Systems-on-Chip. [Citation Graph (0, 0)][DBLP]
    ICCD, 2002, pp:494-499 [Conf]
  93. Luca Benini, Alessandro Bogliolo, Giovanni De Micheli
    Distributed EDA Tool Integration: The PPP Paradigm. [Citation Graph (0, 0)][DBLP]
    ICCD, 1996, pp:448-453 [Conf]
  94. Matteo Dall'Osso, Gianluca Biccari, Luca Giovannini, Davide Bertozzi, Luca Benini
    xpipes: a Latency Insensitive Parameterized Network-on-chip Architecture For Multi-Processor SoCs. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:536-0 [Conf]
  95. Mirko Loghi, Luca Benini, Massimo Poncino
    Analyzing Power Consumption of Message Passing Primitives in a Single-Chip Multiprocessor. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:393-396 [Conf]
  96. Martino Ruggiero, Andrea Acquaviva, Davide Bertozzi, Luca Benini
    Application-Specific Power-Aware Workload Allocation for Voltage Scalable MPSoC Platforms. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:87-93 [Conf]
  97. Elisabetta Farella, Augusto Pieracci, Davide Brunelli, Luca Benini, Bruno Riccò, Andrea Acquaviva
    Design and Implementation of WiMoCA Node for a Body Area Wireless Sensor Network. [Citation Graph (0, 0)][DBLP]
    ICW/ICHSN/ICMCS/SENET, 2005, pp:342-347 [Conf]
  98. Luca Benini, Davide Bertozzi, Alessio Guerri, Michela Milano
    Allocation and Scheduling for MPSoCs via decomposition and no-good generation. [Citation Graph (0, 0)][DBLP]
    IJCAI, 2005, pp:1517-1518 [Conf]
  99. Emanuele Lattanzi, Aman Gayasen, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Luca Benini, Alessandro Bogliolo
    Improving Java Performance Using Dynamic Method Migration on FPGAs. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2004, pp:- [Conf]
  100. Elisa Ficarra, Luca Benini, Bruno Riccò, G. Zuccheri
    Automated DNA sizing in atomic force microscope images. [Citation Graph (0, 0)][DBLP]
    ISBI, 2002, pp:453-456 [Conf]
  101. Nicolas Genko, David Atienza, Giovanni De Micheli, Luca Benini, Jose Manuel Mendias, Román Hermida, Francky Catthoor
    A novel approach for network on chip emulation. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2365-2368 [Conf]
  102. Davide Bertozzi, Luca Benini, Bruno Riccò
    Energy-efficient and reliable low-swing signaling for on-chip buses based on redundant coding. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2002, pp:93-96 [Conf]
  103. Luca Benini, Davide Bruni, Bruno Riccò, Alberto Macii, Enrico Macii
    An adaptive data compression scheme for memory traffic minimization in processor-based systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:866-869 [Conf]
  104. Elisabetta Farella, Augusto Pieracci, Luca Benini, Andrea Acquaviva
    A Wireless Body Area Sensor Network for Posture Detection. [Citation Graph (0, 0)][DBLP]
    ISCC, 2006, pp:454-459 [Conf]
  105. Christine Nardini, Daniele Masotti, Sungroh Yoon, Enrico Macii, Michael D. Kuo, Giovanni De Micheli, Luca Benini
    Mining Gene Sets for Measuring Similarities. [Citation Graph (0, 0)][DBLP]
    ISCC, 2006, pp:227-232 [Conf]
  106. Alessandro Bogliolo, Luca Benini, Bruno Riccò, Giovanni De Micheli
    Efficient switching activity computation during high-level synthesis of control-dominated designs. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1999, pp:127-132 [Conf]
  107. Luca Benini, Angelo Galati, Alberto Macii, Enrico Macii, Massimo Poncino
    Energy-efficient data scrambling on memory-processor interfaces. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2003, pp:26-29 [Conf]
  108. Luca Benini, Robin Hodgson, Polly Siegel
    System-level power estimation and optimization. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:173-178 [Conf]
  109. Luca Benini, Giovanni De Micheli
    Transformation and synthesis of FSMs for low-power gated-clock implementation. [Citation Graph (0, 0)][DBLP]
    ISLPD, 1995, pp:21-26 [Conf]
  110. Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino
    Discharge current steering for battery lifetime optimization. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2002, pp:118-123 [Conf]
  111. Luca Benini, Giovanni De Micheli
    System-level power optimization: techniques and tools. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1999, pp:288-293 [Conf]
  112. Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino
    Selective instruction compression for memory energy reduction in embedded systems. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1999, pp:206-211 [Conf]
  113. Luca Benini, Giovanni De Micheli, Enrico Macii, Massimo Poncino, Stefano Quer
    System-level power optimization of special purpose applications: the beach solution. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1997, pp:24-29 [Conf]
  114. Pietro Babighian, Luca Benini, Alberto Macii, Enrico Macii
    Post-layout leakage power minimization based on distributed sleep transistor insertion. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:138-143 [Conf]
  115. Luca Benini, Alberto Macii, Alberto Nannarelli
    Cached-code compression for energy minimization in embedded processors. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2001, pp:322-327 [Conf]
  116. Luca Benini, Alessandro Bogliolo, Stefano Cavallucci, Bruno Riccò
    Monitoring system activity for OS-directed dynamic power management. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:185-190 [Conf]
  117. Luca Benini, Alberto Macii, Massimo Poncino
    A recursive algorithm for low-power memory partitioning. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2000, pp:78-83 [Conf]
  118. Davide Bertozzi, Luca Benini, Bruno Riccò
    Parametric timing and power macromodels for high level simulation of low-swing interconnects. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2002, pp:307-312 [Conf]
  119. Alessandro Bogliolo, Luca Benini, Giovanni De Micheli, Bruno Riccò
    Gate-level current waveform simulation of CMOS integrated circuits. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:109-112 [Conf]
  120. Eui-Young Chung, Luca Benini, Giovanni De Micheli
    Automatic source code specialization for energy reduction. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2001, pp:80-83 [Conf]
  121. Eui-Young Chung, Giovanni De Micheli, Luca Benini
    Contents provider-assisted dynamic voltage scaling for low energy multimedia applications. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2002, pp:42-47 [Conf]
  122. Michele Favalli, Luca Benini
    Analysis of glitch power dissipation in CMOS ICs. [Citation Graph (0, 0)][DBLP]
    ISLPD, 1995, pp:123-128 [Conf]
  123. Yung-Hsiang Lu, Luca Benini, Giovanni De Micheli
    Operating-system directed power reduction. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2000, pp:37-42 [Conf]
  124. Tajana Simunic, Luca Benini, Giovanni De Micheli
    Energy-efficient design of battery-powered embedded systems. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1999, pp:212-217 [Conf]
  125. Patrick Vuillod, Luca Benini, Alessandro Bogliolo, Giovanni De Micheli
    Clock skew optimization for peak current reduction. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:265-270 [Conf]
  126. Patrick Vuillod, Luca Benini, Giovanni De Micheli
    Re-mapping for low power under tight timing constraints. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1997, pp:287-292 [Conf]
  127. Mirko Loghi, Massimo Poncino, Luca Benini
    Synchronization-driven dynamic speed scaling for MPSoCs. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2006, pp:346-349 [Conf]
  128. Ashutosh Chakraborty, K. Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino
    Dynamic thermal clock skew compensation using tunable delay buffers. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2006, pp:162-167 [Conf]
  129. Luca Benini, Giuliano Castelli, Alberto Macii, Enrico Macii, Riccardo Scarsi
    Battery-Driven Dynamic Power Management of Portable Systems. [Citation Graph (0, 0)][DBLP]
    ISSS, 2000, pp:25-33 [Conf]
  130. Luca Benini, Giovanni De Micheli
    Powering networks on chips. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:33-38 [Conf]
  131. Luca Benini, Patrick Vuillod, Claudionor José Nunes Coelho Jr., Giovanni De Micheli
    Synthesis of Low-Power Selectively-Clocked Systems from High-Level Specification. [Citation Graph (0, 0)][DBLP]
    ISSS, 1996, pp:57-0 [Conf]
  132. Eui-Young Chung, Luca Benini, Giovanni De Micheli
    Source code transformation based on software cost analysis. [Citation Graph (0, 0)][DBLP]
    ISSS, 2001, pp:153-158 [Conf]
  133. Yung-Hsiang Lu, Giovanni De Micheli, Luca Benini
    Requester-Aware Power Reduction. [Citation Graph (0, 0)][DBLP]
    ISSS, 2000, pp:18-24 [Conf]
  134. Tajana Simunic, Giovanni De Micheli, Luca Benini
    Event-Driven Power Management of Portable Systems. [Citation Graph (0, 0)][DBLP]
    ISSS, 1999, pp:18-23 [Conf]
  135. Tajana Simunic, Giovanni De Micheli, Luca Benini, Mat Hans
    Source Code Optimization and Profiling of Energy Consumption in Embedded Systems. [Citation Graph (0, 0)][DBLP]
    ISSS, 2000, pp:193-199 [Conf]
  136. Luca Benini, Davide Bruni, Alberto Macii, Enrico Macii
    Hardw are Implementation of Data Compression Algorithms for Memory Energy Optimization. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2003, pp:250-251 [Conf]
  137. Tajana Simunic, Luca Benini, Peter W. Glynn, Giovanni De Micheli
    Dynamic power management for portable systems. [Citation Graph (0, 0)][DBLP]
    MOBICOM, 2000, pp:11-19 [Conf]
  138. Federico Angiolini, Paolo Meloni, Luca Benini, Salvatore Carta, Luigi Raffo
    Networks on Chips: A Synthesis Perspective. [Citation Graph (0, 0)][DBLP]
    PARCO, 2005, pp:745-752 [Conf]
  139. B. Arts, N. van der Eng, Marc J. M. Heijligers, H. Munk, Frans Theeuwen, Luca Benini, Enrico Macii, A. Milia, Roberto Maro, A. Bellu
    Statistical Power Estimation of Behavioral Descriptions. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2003, pp:197-207 [Conf]
  140. Luca Benini, Alberto Macii, Enrico Macii
    Offline Data Profiling Techniques to Enhance Memory Compression in Embedded Systems. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2002, pp:314-322 [Conf]
  141. Kimish Patel, Luca Benini, Enrico Macii, Massimo Poncino
    Energy-Efficient Value-Based Selective Refresh for Embedded DRAMs. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:466-476 [Conf]
  142. Davide Brunelli, Elisabetta Farella, Laura Rocchi, Marco Dozza, Lorenzo Chiari, Luca Benini
    Bio-feedback System for Rehabilitation Based on a Wireless Body Area Network. [Citation Graph (0, 0)][DBLP]
    PerCom Workshops, 2006, pp:527-531 [Conf]
  143. Elisabetta Farella, M. Sile O'Modhrain, Luca Benini, Bruno Riccò
    Gesture Signature for Ambient Intelligence Applications: A Feasibility Study. [Citation Graph (0, 0)][DBLP]
    Pervasive, 2006, pp:288-304 [Conf]
  144. Manish Verma, Lars Wehmeyer, Robert Pyka, Peter Marwedel, Luca Benini
    Compilation and Simulation Tool Chain for Memory Aware Energy Optimizations . [Citation Graph (0, 0)][DBLP]
    SAMOS, 2006, pp:279-288 [Conf]
  145. Antonio Pullini, Federico Angiolini, Davide Bertozzi, Luca Benini
    Fault tolerance overhead in network-on-chip flow control schemes. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2005, pp:224-229 [Conf]
  146. Luca Benini
    Advanced power management of SoC platforms. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2005, pp:1- [Conf]
  147. Luca Benini
    Energy efficient NoC design. [Citation Graph (0, 0)][DBLP]
    SBCCI, 2005, pp:6- [Conf]
  148. Luca Benini, Sandeep K. Shukla, Rajesh K. Gupta
    Architectural, System Level and Protocol Level Techniques for Power Optimization for Networked Embedded Systems. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:18-0 [Conf]
  149. Nikil Dutt, Kaustav Banerjee, Luca Benini, Kanishka Lahiri, Sudeep Pasricha
    Tutorial 5: SoC Communication Architectures: Technology, Current Practice, Research, and Trends. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:8- [Conf]
  150. Luca Benini, Davide Bertozzi, Davide Bruni, Nicola Drago, Franco Fummi, Massimo Poncino
    SystemC Cosimulation and Emulation of Multiprocessor SoC Designs. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2003, v:36, n:4, pp:53-59 [Journal]
  151. Luca Benini, Giovanni De Micheli
    Networks on Chips: A New SoC Paradigm. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2002, v:35, n:1, pp:70-78 [Journal]
  152. Luca Benini, Giuliano Castelli, Alberto Macii, Riccardo Scarsi
    Battery-Driven Dynamic Power Management. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2001, v:18, n:2, pp:53-60 [Journal]
  153. Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino
    Increasing Energy Efficiency of Embedded Systems by Application-Specific Memory Hierarchy Generation. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2000, v:17, n:2, pp:74-85 [Journal]
  154. Luca Benini, Polly Siegel, Giovanni De Micheli
    Saving Power by Synthesizing Gated Clocks for Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1994, v:11, n:4, pp:32-41 [Journal]
  155. Marcello Dalpasso, Alessandro Bogliolo, Luca Benini
    Virtual Simulation of Distributed IP-Based Designs. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2002, v:19, n:5, pp:92-104 [Journal]
  156. Paul Marchal, Francky Catthoor, Davide Bruni, Luca Benini, José Ignacio Gómez, Luis Piñuel
    Integrated Task Scheduling and Data Assignment for SDRAMs in Dynamic Applications. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2004, v:21, n:5, pp:378-387 [Journal]
  157. Srinivasan Murali, Theo Theocharides, Narayanan Vijaykrishnan, Mary Jane Irwin, Luca Benini, Giovanni De Micheli
    Analysis of Error Recovery Schemes for Networks on Chips. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:5, pp:434-442 [Journal]
  158. Luca Benini, Davide Bertozzi, Alessio Guerri, Michela Milano, Francesco Poletti
    Measuring Efficiency and Executability of Allocation and Scheduling in Multi-Processor Systems-on-Chip. [Citation Graph (0, 0)][DBLP]
    Intelligenza Artificiale, 2005, v:2, n:3, pp:13-20 [Journal]
  159. Elisabetta Farella, Davide Brunelli, Luca Benini, Bruno Riccò, Maria Elena Bonfigli
    Pervasive Computing for Interactive Virtual Heritage. [Citation Graph (0, 0)][DBLP]
    IEEE MultiMedia, 2005, v:12, n:3, pp:46-58 [Journal]
  160. Daniele Masotti, Elisa Ficarra, Enrico Macii, Luca Benini
    Optimized Technique for Dna Structural Properties Discovering. [Citation Graph (0, 0)][DBLP]
    International Journal on Artificial Intelligence Tools, 2006, v:15, n:5, pp:695-710 [Journal]
  161. David Atienza, Stylianos Mamagkakis, Francesco Poletti, Jose Manuel Mendias, Francky Catthoor, Luca Benini, Dimitrios Soudris
    Efficient system-level prototyping of power-aware dynamic memory managers for embedded systems. [Citation Graph (0, 0)][DBLP]
    Integration, 2006, v:39, n:2, pp:113-130 [Journal]
  162. Luca Benini
    Guest Editorial. [Citation Graph (0, 0)][DBLP]
    Integration, 2004, v:38, n:1, pp:1-2 [Journal]
  163. Terry Tao Ye, Luca Benini, Giovanni De Micheli
    Packetization and routing analysis of on-chip multiprocessor networks. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2004, v:50, n:2-3, pp:81-104 [Journal]
  164. Simona Rossi, Daniele Masotti, Christine Nardini, Elena Bonora, Giovanni Romeo, Enrico Macii, Luca Benini, Stefano Volinia
    TOM: a web-based integrated approach for identification of candidate disease genes. [Citation Graph (0, 0)][DBLP]
    Nucleic Acids Research, 2006, v:34, n:Web-Server-Issue, pp:285-292 [Journal]
  165. Andrea Acquaviva, Luca Benini, Bruno Riccò
    Energy characterization of embedded real-time operating systems. [Citation Graph (0, 0)][DBLP]
    SIGARCH Computer Architecture News, 2001, v:29, n:5, pp:13-18 [Journal]
  166. Luca Benini, Davide Bruni, Alberto Macii, Enrico Macii, Massimo Poncino
    Discharge Current Steering for Battery Lifetime Optimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2003, v:52, n:8, pp:985-995 [Journal]
  167. Luca Benini, Giovanni De Micheli, Antonio Lioy, Enrico Macii, Giuseppe Odasso, Massimo Poncino
    Automatic Synthesis of Large Telescopic Units Based on Near-Minimum Timed Supersetting. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1999, v:48, n:8, pp:769-779 [Journal]
  168. Luca Benini, Francesco Menichelli, Mauro Olivieri
    A Class of Code Compression Schemes for Reducing Power Consumption in Embedded Microprocessor Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2004, v:53, n:4, pp:467-482 [Journal]
  169. Eui-Young Chung, Luca Benini, Alessandro Bogliolo, Yung-Hsiang Lu, Giovanni De Micheli
    Dynamic Power Management for Nonstationary Service Requests. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2002, v:51, n:11, pp:1345-1361 [Journal]
  170. Francesco Poletti, Antonio Poggiali, Davide Bertozzi, Luca Benini, Pol Marchal, Mirko Loghi, Massimo Poncino
    Energy-Efficient Multiprocessor Systems-on-Chip for Embedded Computing: Exploring Programming Models and Their Architectural Support. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2007, v:56, n:5, pp:606-621 [Journal]
  171. Andrea Acquaviva, Luca Benini, Bruno Riccò
    Software-controlled processor speed setting for low-power streamingmultimedia. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:11, pp:1283-1292 [Journal]
  172. Federico Angiolini, Luca Benini, Alberto Caprara
    An efficient profile-based algorithm for scratchpad memory partitioning. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:11, pp:1660-1676 [Journal]
  173. Pietro Babighian, Luca Benini, Enrico Macii
    A scalable algorithm for RTL insertion of gated clocks based on ODCs computation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:1, pp:29-42 [Journal]
  174. Davide Bertozzi, Luca Benini, Giovanni De Micheli
    Error control schemes for on-chip communication links: the energy-reliability tradeoff. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:6, pp:818-831 [Journal]
  175. Luca Benini, Alessandro Bogliolo, Giuseppe A. Paleologo, Giovanni De Micheli
    Policy optimization for dynamic power management. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:6, pp:813-833 [Journal]
  176. Luca Benini, Giovanni De Micheli
    Automatic synthesis of low-power gated-clock finite-state machines. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:6, pp:630-643 [Journal]
  177. Luca Benini, Giovanni De Micheli, Antonio Lioy, Enrico Macii, Giuseppe Odasso, Massimo Poncino
    Synthesis of power-managed sequential components based oncomputational kernel extraction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:9, pp:1118-1131 [Journal]
  178. Luca Benini, Giovanni De Micheli, Enrico Macii, Massimo Poncino, Riccardo Scarsi
    A multilevel engine for fast power simulation of realistic inputstreams. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:4, pp:459-472 [Journal]
  179. Luca Benini, Enrico Macii, Massimo Poncino, Giovanni De Micheli
    Telescopic units: a new paradigm for performance optimization of VLSI designs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:3, pp:220-232 [Journal]
  180. Luca Benini, Alberto Macii, Massimo Poncino, Riccardo Scarsi
    Architectures and synthesis algorithms for power-efficient businterfaces. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:9, pp:969-980 [Journal]
  181. Luca Benini, Patrick Vuillod, Giovanni De Micheli
    Iterative remapping for logic circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:10, pp:948-964 [Journal]
  182. Eui-Young Chung, Luca Benini, Giovanni De Micheli, Gabriele Luculli, Marco Carilli
    Value-sensitive automatic code specialization for embedded software. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:9, pp:1051-1067 [Journal]
  183. Yung-Hsiang Lu, Luca Benini, Giovanni De Micheli
    Dynamic frequency scaling with buffer insertion for mixed workloads. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:11, pp:1284-1305 [Journal]
  184. Tajana Simunic, Luca Benini, Peter W. Glynn, Giovanni De Micheli
    Event-driven power management. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:7, pp:840-857 [Journal]
  185. Sungroh Yoon, Luca Benini, Giovanni De Micheli
    A Pattern-Mining Method for High-Throughput Lab-on-a-Chip Data Analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:2, pp:358-377 [Journal]
  186. Sungroh Yoon, Christine Nardini, Luca Benini, Giovanni De Micheli
    Discovering Coherent Biclusters from Gene Expression Data Using Zero-Suppressed Binary Decision Diagrams. [Citation Graph (0, 0)][DBLP]
    IEEE/ACM Trans. Comput. Biology Bioinform., 2005, v:2, n:4, pp:339-354 [Journal]
  187. Luca Benini, Alberto Macii, Massimo Poncino
    Energy-aware design of embedded memories: A survey of technologies, architectures, and optimization techniques. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2003, v:2, n:1, pp:5-32 [Journal]
  188. Mirko Loghi, Massimo Poncino, Luca Benini
    Cache coherence tradeoffs in shared-memory MPSoCs. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2006, v:5, n:2, pp:383-407 [Journal]
  189. Elisa Ficarra, Luca Benini, Enrico Macii, G. Zuccheri
    Automated DNA fragments recognition and sizing through AFM image processing. [Citation Graph (0, 0)][DBLP]
    IEEE Transactions on Information Technology in Biomedicine, 2005, v:9, n:4, pp:508-517 [Journal]
  190. Luca Benini, Giovanni De Micheli
    System-level power optimization: techniques and tools. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2000, v:5, n:2, pp:115-192 [Journal]
  191. Luca Benini, Giovanni De Micheli
    Synthesis of low-power selectively-clocked systems from high-level specification. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2000, v:5, n:3, pp:311-321 [Journal]
  192. Luca Benini, Giovanni De Micheli
    A survey of Boolean matching techniques for library binding. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1997, v:2, n:3, pp:193-226 [Journal]
  193. Luca Benini, Giovanni De Micheli, Enrico Macii, Massimo Poncino, Riccardo Scarsi
    Symbolic synthesis of clock-gating logic for power optimization of synchronous controllers. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1999, v:4, n:4, pp:351-375 [Journal]
  194. Alessandro Bogliolo, Luca Benini, Giovanni De Micheli
    Regression-based RTL power modeling. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2000, v:5, n:3, pp:337-372 [Journal]
  195. Davide Bertozzi, Antoine Jalabert, Srinivasan Murali, Rutuparna Tamhankar, Stergios Stergiou, Luca Benini, Giovanni De Micheli
    NoC Synthesis Flow for Customized Domain Specific Multiprocessor Systems-on-Chip. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2005, v:16, n:2, pp:113-129 [Journal]
  196. Luca Benini, Davide Bruni, Alberto Macii, Enrico Macii
    Memory energy minimization by data compression: algorithms, architectures and implementation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:3, pp:255-268 [Journal]
  197. Luca Benini, Elisabetta Farella, Carlotta Guiducci
    Wireless sensor networks: Enabling technology for ambient intelligence. [Citation Graph (0, 0)][DBLP]
    Microelectronics Journal, 2006, v:37, n:12, pp:1639-1649 [Journal]
  198. Andrea Marongiu, Luca Benini, Mahmut T. Kandemir
    Lightweight barrier-based parallelization support for non-cache-coherent MPSoC platforms. [Citation Graph (0, 0)][DBLP]
    CASES, 2007, pp:145-149 [Conf]
  199. A. Sathanur, Andrea Calimera, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino
    Interactive presentation: Efficient computation of discharge current upper bounds for clustered sleep transistor sizing. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:1544-1549 [Conf]
  200. Simone Medardoni, Martino Ruggiero, Davide Bertozzi, Luca Benini, Giovanni Strano, Carlo Pistritto
    Interactive presentation: Capturing the interaction of the communication, memory and I/O subsystems in memory-centric industrial MPSoC platforms. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:660-665 [Conf]
  201. Ani Nahapetian, Paolo Lombardo, Andrea Acquaviva, Luca Benini, Majid Sarrafzadeh
    Dynamic reconfiguration in sensor networks with regenerative energy sources. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:1054-1059 [Conf]
  202. Clemens Moser, Lothar Thiele, Davide Brunelli, Luca Benini
    Adaptive power management in energy harvesting systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:773-778 [Conf]
  203. Federico Angiolini, M. Haykel Ben Jamaa, David Atienza, Luca Benini, Giovanni De Micheli
    Interactive presentation: Improving the fault tolerance of nanometric PLA designs. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:570-575 [Conf]
  204. Clemens Moser, Davide Brunelli, Lothar Thiele, Luca Benini
    Lazy Scheduling for Energy Harvesting Sensor Nodes. [Citation Graph (0, 0)][DBLP]
    DIPES, 2006, pp:125-134 [Conf]
  205. Stefano Baraldi, Alberto Del Bimbo, Lea Landucci, Nicola Torpei, Omar Cafini, Elisabetta Farella, Augusto Pieracci, Luca Benini
    Introducing tangerine: a tangible interactive natural environment. [Citation Graph (0, 0)][DBLP]
    ACM Multimedia, 2007, pp:831-834 [Conf]
  206. Shankar Mahadevan, Federico Angiolini, Jens Sparsø, Luca Benini, Jan Madsen
    A Traffic Injection Methodology with Support for System-Level Synchronization. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2005, pp:145-161 [Conf]
  207. Srinivasan Murali, Paolo Meloni, Federico Angiolini, David Atienza, Salvatore Carta, Luca Benini, Giovanni De Micheli, Luigi Raffo
    Designing Message-Dependent Deadlock Free Networks on Chips for Application-Specific Systems on Chips. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:158-163 [Conf]
  208. Pablo Garcia Del Valle, David Atienza, Ivan Magan, Javier Garcia Flores, Esther Andres Perez, Jose Manuel Mendias, Luca Benini, Giovanni De Micheli
    A Complete Multi-Processor System-on-Chip FPGA-Based Emulation Framework. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:140-145 [Conf]
  209. Simon Ogg, Enrico Valli, Crescenzo D'Alessandro, Alexandre Yakovlev, Bashir M. Al-Hashimi, Luca Benini
    Reducing Interconnect Cost in NoC through Serialized Asynchronous Links. [Citation Graph (0, 0)][DBLP]
    NOCS, 2007, pp:219- [Conf]
  210. Antonio Pullini, Federico Angiolini, Paolo Meloni, David Atienza, Srinivasan Murali, Luigi Raffo, Giovanni De Micheli, Luca Benini
    NoC Design and Implementation in 65nm Technology. [Citation Graph (0, 0)][DBLP]
    NOCS, 2007, pp:273-282 [Conf]
  211. Antonio Pullini, Federico Angiolini, Srinivasan Murali, David Atienza, Giovanni De Micheli, Luca Benini
    Bringing NoCs to 65 nm. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2007, v:27, n:5, pp:75-85 [Journal]
  212. Salvatore Carta, Andrea Alimonda, Alessandro Pisano, Andrea Acquaviva, Luca Benini
    A control theoretic approach to energy-efficient pipelined computation in MPSoCs. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2007, v:6, n:4, pp:- [Journal]
  213. Mirko Loghi, Luca Benini, Massimo Poncino
    Power macromodeling of MPSoC message passing primitives. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2007, v:6, n:4, pp:- [Journal]
  214. David Atienza, Pablo Garcia Del Valle, Giacomo Paci, Francesco Poletti, Luca Benini, Giovanni De Micheli, Jose Manuel Mendias, Román Hermida
    HW-SW emulation framework for temperature-aware design in MPSoCs. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2007, v:12, n:3, pp:- [Journal]
  215. Srinivasan Murali, David Atienza, Paolo Meloni, Salvatore Carta, Luca Benini, Giovanni De Micheli, Luigi Raffo
    Synthesis of Predictable Networks-on-Chip-Based Interconnect Architectures for Chip Multiprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:8, pp:869-880 [Journal]
  216. Alessandro Bogliolo, Luca Benini, Giovanni De Micheli, Bruno Riccò
    Gate-level power and current simulation of CMOS integrated circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1997, v:5, n:4, pp:473-488 [Journal]
  217. Luca Benini, Giovanni De Micheli, Enrico Macii, Massimo Poncino, Stefano Quer
    Power optimization of core-based systems by address bus encoding. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:4, pp:554-562 [Journal]
  218. Alessandro Bogliolo, Luca Benini
    Robust RTL power macromodels. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:4, pp:578-581 [Journal]
  219. Luca Benini, Giovanni De Micheli, Alberto Macii, Enrico Macii, Massimo Poncino, Riccardo Scarsi
    Glitch power minimization by selective gate freezing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:3, pp:287-298 [Journal]
  220. Luca Benini, Alessandro Bogliolo, Giovanni De Micheli
    A survey of design techniques for system-level dynamic power management. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:3, pp:299-316 [Journal]
  221. Tajana Simunic, Luca Benini, Giovanni De Micheli
    Energy-efficient design of battery-powered embedded systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:1, pp:15-28 [Journal]
  222. Luca Benini, Giuliano Castelli, Alberto Macii, Enrico Macii, Massimo Poncino, Riccardo Scarsi
    Discrete-time battery models for system-level low-power design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:5, pp:630-640 [Journal]
  223. Yung-Hsiang Lu, Luca Benini, Giovanni De Micheli
    Power-aware operating systems for interactive systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:2, pp:119-134 [Journal]
  224. Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino
    Minimizing memory access energy in embedded systems by selective instruction compression. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:5, pp:521-531 [Journal]
  225. Luca Benini, Luca Macchiarulo, Alberto Macii, Massimo Poncino
    Layout-driven memory synthesis for embedded systems-on-chip. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:2, pp:96-105 [Journal]
  226. Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino, Riccardo Scarsi
    Scheduling battery usage in mobile systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:6, pp:1136-1143 [Journal]
  227. Vivek De, Luca Benini
    Guest editorial. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:5, pp:753-754 [Journal]
  228. Kimish Patel, Enrico Macii, Massimo Poncino, Luca Benini
    Energy-Efficient Value Based Selective Refresh for Embedded DRAMS. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2006, v:2, n:1, pp:70-79 [Journal]

  229. Exploration of Low Power Adders for a SIMD Data Path. [Citation Graph (, )][DBLP]


  230. Reliability-aware design for nanometer-scale devices. [Citation Graph (, )][DBLP]


  231. Synthesis of networks on chips for 3D systems on chips. [Citation Graph (, )][DBLP]


  232. Multimodal Abandoned/Removed Object Detection for Low Power Video Surveillance Systems. [Citation Graph (, )][DBLP]


  233. Enhancing the spatial resolution of presence detection in a PIR based wireless surveillance network. [Citation Graph (, )][DBLP]


  234. Distributed video surveillance using hardware-friendly sparse large margin classifiers. [Citation Graph (, )][DBLP]


  235. Methods for Designing Reliable Probe Arrays. [Citation Graph (, )][DBLP]


  236. Predictability vs. Efficiency in the Multicore Era: Fight of Titans or Happy Ever after?. [Citation Graph (, )][DBLP]


  237. Variability-tolerant run-time workload allocation for MPSoC energy minimization under real-time constraints. [Citation Graph (, )][DBLP]


  238. Evolving tuis with smart objects for multi-context interaction. [Citation Graph (, )][DBLP]


  239. Performance analysis and design space exploration for high-end biomedical applications: challenges and solutions. [Citation Graph (, )][DBLP]


  240. Minimization of the reconfiguration latency for the mapping of applications on FPGA-based systems. [Citation Graph (, )][DBLP]


  241. A Constraint Programming Approach for Allocation and Scheduling on the CELL Broadband Engine. [Citation Graph (, )][DBLP]


  242. Multi-stage Benders Decomposition for Optimizing Multicore Architectures. [Citation Graph (, )][DBLP]


  243. Throughput Constraint for Synchronous Data Flow Graphs. [Citation Graph (, )][DBLP]


  244. NoC topology synthesis for supporting shutdown of voltage islands in SoCs. [Citation Graph (, )][DBLP]


  245. Networks on Chips: from research to products. [Citation Graph (, )][DBLP]


  246. 07041 Abstracts Collection - Power-aware Computing Systems. [Citation Graph (, )][DBLP]


  247. 07041 Summary - Power-aware Computing Systems. [Citation Graph (, )][DBLP]


  248. Temperature Control of High-Performance Multi-core Platforms Using Convex Optimization. [Citation Graph (, )][DBLP]


  249. Thermal Balancing Policy for Streaming Computing on Multiprocessor Architectures. [Citation Graph (, )][DBLP]


  250. Serialized Asynchronous Links for NoC. [Citation Graph (, )][DBLP]


  251. HOT TOPIC - 3D Integration or How to Scale in the 21st Century. [Citation Graph (, )][DBLP]


  252. An Efficient Solar Energy Harvester for Wireless Sensor Nodes. [Citation Graph (, )][DBLP]


  253. Process Variation Tolerant Pipeline Design Through a Placement-Aware Multiple Voltage Island Design Style. [Citation Graph (, )][DBLP]


  254. Developing Mesochronous Synchronizers to Enable 3D NoCs. [Citation Graph (, )][DBLP]


  255. A Scalable Algorithmic Framework for Row-Based Power-Gating. [Citation Graph (, )][DBLP]


  256. Robust and Low Complexity Rate Control for Solar Powered Sensors. [Citation Graph (, )][DBLP]


  257. Optimal MTCMOS Reactivation Under Power Supply Noise and Performance Constraints. [Citation Graph (, )][DBLP]


  258. Adaptive least mean square behavioral power modeling. [Citation Graph (, )][DBLP]


  259. Symbolic synthesis of clock-gating logic for power optimization of control-oriented synchronous networks. [Citation Graph (, )][DBLP]


  260. System-level power/performance evaluation of 3D stacked DRAMs for mobile applications. [Citation Graph (, )][DBLP]


  261. Effectiveness of adaptive supply voltage and body bias as post-silicon variability compensation techniques for full-swing and low-swing on-chip communication channels. [Citation Graph (, )][DBLP]


  262. SunFloor 3D: A tool for Networks On Chip topology synthesis for 3D systems on chips. [Citation Graph (, )][DBLP]


  263. Robust non-preemptive hard real-time scheduling for clustered multicore platforms. [Citation Graph (, )][DBLP]


  264. Adaptive idleness distribution for non-uniform aging tolerance in MultiProcessor Systems-on-Chip. [Citation Graph (, )][DBLP]


  265. Physically clustered forward body biasing for variability compensation in nanometer CMOS design. [Citation Graph (, )][DBLP]


  266. Synthesis of low-overhead configurable source routing tables for network interfaces. [Citation Graph (, )][DBLP]


  267. Efficient OpenMP support and extensions for MPSoCs with explicitly managed memory hierarchy. [Citation Graph (, )][DBLP]


  268. Visual quality analysis for dynamic backlight scaling in LCD systems. [Citation Graph (, )][DBLP]


  269. Efficient OpenMP data mapping for multicore platforms with vertically stacked memory. [Citation Graph (, )][DBLP]


  270. Design space exploration of a mesochronous link for cost-effective and flexible GALS NOCs. [Citation Graph (, )][DBLP]


  271. An efficient and complete approach for throughput-maximal SDF allocation and scheduling on multi-core platforms. [Citation Graph (, )][DBLP]


  272. A method to remove deadlocks in Networks-on-Chips with Wormhole flow control. [Citation Graph (, )][DBLP]


  273. Parallel subdivision surface rendering and animation on the Cell BE processor. [Citation Graph (, )][DBLP]


  274. An efficient distributed memory interface for many-core platform with 3D stacked DRAM. [Citation Graph (, )][DBLP]


  275. Cellflow: A Parallel Application Development Environment with Run-Time Support for the Cell BE Processor. [Citation Graph (, )][DBLP]


  276. Analysis of Power Management Strategies for a Large-Scale SoC Platform in 65nm Technology. [Citation Graph (, )][DBLP]


  277. How to Live with Uncertainties: Exploiting the Performance Benefits of Self-Timed Logic In Synchronous Design. [Citation Graph (, )][DBLP]


  278. A Solar-powered Video Sensor Node for Energy Efficient Multimodal Surveillance. [Citation Graph (, )][DBLP]


  279. Real-Time Scheduling with Regenerative Energy. [Citation Graph (, )][DBLP]


  280. Communication-aware stochastic allocation and scheduling framework for conditional task graphs in multi-processor systems-on-chip. [Citation Graph (, )][DBLP]


  281. DBS4video: dynamic luminance backlight scaling based on multi-histogram frame characterization for video streaming application. [Citation Graph (, )][DBLP]


  282. HVS-DBS: human visual system-aware dynamic luminance backlight scaling for video streaming applications. [Citation Graph (, )][DBLP]


  283. MP-Queue: an Efficient Communication Library for Embedded Streaming Multimedia Platforms. [Citation Graph (, )][DBLP]


  284. Variability-tolerant workload allocation for MPSoC energy minimization under real-time constraints. [Citation Graph (, )][DBLP]


  285. Analysis of Audio Streaming Capability of Zigbee Networks. [Citation Graph (, )][DBLP]


  286. Activity Recognition from On-Body Sensors: Accuracy-Power Trade-Off by Dynamic Sensor Selection. [Citation Graph (, )][DBLP]


  287. Optimal sleep transistor synthesis under timing and area constraints. [Citation Graph (, )][DBLP]


  288. Capturing topology-level implications of link synthesis techniques for nanoscale networks-on-chip. [Citation Graph (, )][DBLP]


  289. A new physical routing approach for robust bundled signaling on NoC links. [Citation Graph (, )][DBLP]


  290. A virtual platform environment for exploring power, thermal and reliability management control strategies in high-performance multicores. [Citation Graph (, )][DBLP]


  291. Approximate Control Design for Solar Driven Sensor Nodes. [Citation Graph (, )][DBLP]


  292. A low-overhead fault tolerance scheme for TSV-based 3D network on chip links. [Citation Graph (, )][DBLP]


  293. A method for calculating hard QoS guarantees for Networks-on-Chip. [Citation Graph (, )][DBLP]


  294. Reliability Support for On-Chip Memories Using Networks-on-Chip. [Citation Graph (, )][DBLP]


  295. Resource Management Policy Handling Multiple Use-Cases in MPSoC Platforms Using Constraint Programming. [Citation Graph (, )][DBLP]


  296. Hidden Markov Models Implementation for Tangible Interfaces. [Citation Graph (, )][DBLP]


  297. On quantifying the figures of merit of power-gating for leakage power minimization in nanometer CMOS circuits. [Citation Graph (, )][DBLP]


  298. Multiple power-gating domain (multi-VGND) architecture for improved leakage power reduction. [Citation Graph (, )][DBLP]


  299. Timing-driven row-based power gating. [Citation Graph (, )][DBLP]


  300. Automatic synthesis of near-threshold circuits with fine-grained performance tunability. [Citation Graph (, )][DBLP]


  301. Temporal Discharge Current Driven Clustering for Improved Leakage Power Reduction in Row-Based Power-Gating. [Citation Graph (, )][DBLP]


  302. A smart wireless glove for gesture interaction. [Citation Graph (, )][DBLP]


  303. OpenMP Support for NBTI-Induced Aging Tolerance in MPSoCs. [Citation Graph (, )][DBLP]


  304. Comparing tightly and loosely coupled mesochronous synchronizers in a NoC switch architecture. [Citation Graph (, )][DBLP]


  305. Exploring High-Dimensional Topologies for NoC Design Through an Integrated Analysis and Synthesis Framework. [Citation Graph (, )][DBLP]


  306. Statistical Significance in Omic Data Analyses - Alternative/Complementary Method for Efficient Automatic Identification of Statistically Significant Tests in High Throughput Biological Studies. [Citation Graph (, )][DBLP]


  307. MM-Correction: Meta-analysis-Based Multiple Hypotheses Correction in Omic Studies. [Citation Graph (, )][DBLP]


  308. A High-Performance Wireless Sensor Node for Industrial Control Applications. [Citation Graph (, )][DBLP]


  309. Designing Regular Network-on-Chip Topologies under Technology, Architecture and Software Constraints. [Citation Graph (, )][DBLP]


  310. Scalable instruction set simulator for thousand-core architectures running on GPGPUs. [Citation Graph (, )][DBLP]


  311. TOM: enhancement and extension of a tool suite for in silico approaches to multigenic hereditary disorders. [Citation Graph (, )][DBLP]


  312. Electronic Detection of DNA Hybridization: Toward CMOS Microarrays. [Citation Graph (, )][DBLP]


  313. The State of ESL Design [Roundtable]. [Citation Graph (, )][DBLP]


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