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Georges G. E. Gielen: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Ewout Martens, Georges G. E. Gielen
    High-level modeling of continuous-time Delta-Sigma A/D-converters using formal models. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2004, pp:51-56 [Conf]
  2. Huiying Yang, Mukesh Ranjan, Wim Verhaegen, Mengmeng Ding, Ranga Vemuri, Georges G. E. Gielen
    Efficient symbolic sensitivity analysis of analog circuits using element-coefficient diagrams. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2005, pp:230-235 [Conf]
  3. Mustafa Badaroglu, Kris Tiri, Stéphane Donnay, Piet Wambacq, Hugo De Man, Ingrid Verbauwhede, Georges G. E. Gielen
    Clock tree optimization in synchronous CMOS digital circuits for substrate noise reduction using folding of supply current transients. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:399-404 [Conf]
  4. Ovidiu Bajdechi, Johan H. Huijsing, Georges G. E. Gielen
    Optimal design of delta-sigma ADCs by design space exploration. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:443-448 [Conf]
  5. L. Richard Carley, Georges G. E. Gielen, Rob A. Rutenbar, Willy M. C. Sansen
    Synthesis Tools for Mixed-Signal ICs: Progress on Frontend and Backend Strategies. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:298-303 [Conf]
  6. Walter Daems, Georges G. E. Gielen, Willy M. C. Sansen
    An efficient optimization--based technique to generate posynomial performance models for analog integrated circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:431-436 [Conf]
  7. Walter Daems, Georges G. E. Gielen, Willy M. C. Sansen
    Circuit Complexity Reduction for Symbolic Analysis of Analog Integrated Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:958-963 [Conf]
  8. Tom Eeckelaert, Raf Schoofs, Georges G. E. Gielen, Michiel Steyaert, Willy M. C. Sansen
    Hierarchical bottom--up analog optimization methodology validated by a delta-sigma A/D converter design for the 802.11a/b/g standard. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:25-30 [Conf]
  9. Georges G. E. Gielen, Trent McConaghy, Tom Eeckelaert
    Performance space modeling for hierarchical synthesis of analog integrated circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:881-886 [Conf]
  10. Georges G. E. Gielen, Mike Sottak, Mike Murray, Linda Kaye, Maria del Mar Hershenson, Kenneth S. Kundert, Philippe Magarshack, Akria Matsuzawa, Ronald A. Rohrer, Ping Yang
    Panel: When Will the Analog Design Flow Catch Up with Digital Methodology? [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:419- [Conf]
  11. Koen Lampaert, Georges G. E. Gielen, Willy M. C. Sansen
    Direct Performance-Driven Placement of Mismatch-Sensitive Analog Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:445-449 [Conf]
  12. Stephan Ohr, Rob A. Rutenbar, Henry Chang, Georges G. E. Gielen, Rudolf Koch, Roy McGuffin, K. C. Murphy
    Survival strategies for mixed-signal systems-on-chip (panel session). [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:579-580 [Conf]
  13. Geert Van der Plas, Mustafa Badaroglu, Gerd Vandersteen, Petr Dobrovolný, Piet Wambacq, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man
    High-level simulation of substrate noise in high-ohmic substrates with interconnect and supply effects. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:854-859 [Conf]
  14. Geert Van der Plas, Jan Vandenbussche, Walter Daems, Antal van den Bosch, Georges G. E. Gielen, Willy M. C. Sansen
    Systematic design of a 14-bit 150-MS/s CMOS current-steering D/A converter. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:452-457 [Conf]
  15. Carl De Ranter, B. De Muer, Geert Van der Plas, Peter J. Vancorenland, Michiel Steyaert, Georges G. E. Gielen, Willy M. C. Sansen
    CYCLONE: automated design and layout of RF LC-oscillators. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:11-14 [Conf]
  16. Piet Vanassche, Georges G. E. Gielen, Willy M. C. Sansen
    Behavioral modeling of (coupled) harmonic oscillators. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:536-541 [Conf]
  17. Peter J. Vancorenland, Carl De Ranter, Michiel Steyaert, Georges G. E. Gielen
    Optimal RF design using smart evolutionary algorithms. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:7-10 [Conf]
  18. Jan Vandenbussche, K. Uyttenhove, Erik Lauwers, Michiel Steyaert, Georges G. E. Gielen
    Systematic design of a 200 MS/s 8-bit interpolating/averaging A/D converter. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:449-454 [Conf]
  19. Wim Verhaegen, Georges G. E. Gielen
    Efficient DDD-based Symbolic Analysis of Large Linear Analog Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:139-144 [Conf]
  20. Martin Vogels, Georges G. E. Gielen
    Architectural selection of A/D converters. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:974-977 [Conf]
  21. Mustafa Badaroglu, Marc van Heijningen, Vincent Gravot, Stéphane Donnay, Hugo De Man, Georges G. E. Gielen, Marc Engels, Ivo Bolsens
    High-level simulation of substrate noise generation from large digital circuits with multiple supplies. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:326-330 [Conf]
  22. Mustafa Badaroglu, Piet Wambacq, Geert Van der Plas, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man
    Digital Ground Bounce Reduction by Phase Modulation of the Clock. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:88-93 [Conf]
  23. Walter Daems, Georges G. E. Gielen, Willy M. C. Sansen
    A Fitting Approach to Generate Symbolic Expressions for Linear and Nonlinear Analog Circuit Performance Characteristics. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:268-273 [Conf]
  24. Wolfgang Eberle, Gerd Vandersteen, Piet Wambacq, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man
    Behavioral Modeling and Simulation of a Mixed Analog/Digital Automatic Gain Control Loop in a 5 GHz WLAN Receiver. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10642-10649 [Conf]
  25. Tom Eeckelaert, Walter Daems, Georges G. E. Gielen, Willy M. C. Sansen
    Generalized Posynomial Performance Modeling. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10250-10255 [Conf]
  26. Tom Eeckelaert, Trent McConaghy, Georges G. E. Gielen
    Efficient Multiobjective Synthesis of Analog Circuits using Hierarchical Pareto-Optimal Performance Hypersurfaces. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1070-1075 [Conf]
  27. Kenneth Francken, Martin Vogels, Ewout Martens, Georges G. E. Gielen
    DAISY-CT: A High-Level Simulation Tool for Continuous-Time Delta Sigma Modulators. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:1110- [Conf]
  28. Georges G. E. Gielen, Wim Dehaene, Phillip Christie, Dieter Draxelmayr, Edmond Janssens, Karen Maex, Ted Vucurevich
    Analog and Digital Circuit Design in 65 nm CMOS: End of the Road? [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:36-42 [Conf]
  29. Georges G. E. Gielen, B. Sorensen, H. Casier, Philippe Magarshack, J. Rodriguez
    Design challenges and emerging EDA solutions in mixed-signal IC design. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:694-695 [Conf]
  30. Tholom Kiely, Georges G. E. Gielen
    Performance Modeling of Analog Integrated Circuits Using Least-Squares Support Vector Machines. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:448-453 [Conf]
  31. Erik Lauwers, Georges G. E. Gielen
    A Power Estimation Model for High-Speed CMOS A/D Converters. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:401-405 [Conf]
  32. Ewout Martens, Georges G. E. Gielen
    Top-down heterogeneous synthesis of analog and mixed-signal systems. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:275-280 [Conf]
  33. Ewout Martens, Georges G. E. Gielen
    A Model of Computation for Continuous-Time ?-? Modulators. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10162-10167 [Conf]
  34. Ewout Martens, Georges G. E. Gielen
    A Phase-Frequency Transfer Description of Analog and Mixed-Signal Front-End Architectures for System-Level Design. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:436-441 [Conf]
  35. Ewout Martens, Georges G. E. Gielen
    Time-Domain Simulation of Sampled Weakly Nonlinear Systems Using Analytical Integration and Orthogonal Polynomial Series. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:120-125 [Conf]
  36. Trent McConaghy, Tom Eeckelaert, Georges G. E. Gielen
    CAFFEINE: Template-Free Symbolic Model Generation of Analog Circuits via Canonical Form Functions and Genetic Programming. [Citation Graph (0, 0)][DBLP]
    DATE, 2005, pp:1082-1087 [Conf]
  37. Trent McConaghy, Georges G. E. Gielen
    Double-strength CAFFEINE: fast template-free symbolic modeling of analog circuits via implicit canonical form functions and explicit introns. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:269-274 [Conf]
  38. Mukesh Ranjan, Wim Verhaegen, Anuradha Agarwal, Hemanth Sampath, Ranga Vemuri, Georges G. E. Gielen
    Fast, Layout-Inclusive Analog Circuit Synthesis using Pre-Compiled Parasitic-Aware Symbolic Performance Models. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:604-609 [Conf]
  39. Bart De Smedt, Georges G. E. Gielen
    HOLMES: Capturing the Yield-Optimized Design Space Boundaries of Analog and RF Integrated Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10256-10263 [Conf]
  40. Piet Vanassche, Georges G. E. Gielen, Willy M. C. Sansen
    Efficient time-domain simulation of telecom frontends using a complex damped exponential signal model. [Citation Graph (0, 0)][DBLP]
    DATE, 2001, pp:169-175 [Conf]
  41. Piet Vanassche, Georges G. E. Gielen, Willy M. C. Sansen
    Constructing Symbolic Models for the Input/Output Behavior of Periodically Time-Varying Systems Using Harmonic Transfer Matrices. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:279-284 [Conf]
  42. Piet Vanassche, Georges G. E. Gielen, Willy M. C. Sansen
    Time-Varying, Frequency-Domain Modeling and Analysis of Phase-Locked Loops with Sampling Phase-Frequency Detectors. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10238-10243 [Conf]
  43. Jan Vandenbussche, Stéphane Donnay, Francky Leyn, Georges G. E. Gielen, Willy M. C. Sansen
    Hierarchical Top-Down Design of Analog Sensor Interfaces: From System-Level Specifications Down to Silicon. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:716-720 [Conf]
  44. Jan Vandenbussche, Erik Lauwers, K. Uyttenhove, Michiel Steyaert, Georges G. E. Gielen
    Systematic Design of a 200 Ms/S 8-bit Interpolating A/D Converter. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:357-361 [Conf]
  45. Martin Vogels, Georges G. E. Gielen
    Figure of Merit Based Selection of A/D Converters. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:11090-11091 [Conf]
  46. Stéphane Donnay, Koen Swings, Georges G. E. Gielen, Willy M. C. Sansen, Wim Kruiskamp, Domine Leenaerts
    A Methodology for Analog Design Automation in Mixed-Signal ASICs. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:530-534 [Conf]
  47. Trent McConaghy, Georges G. E. Gielen
    Canonical form functions as a simple means for genetic programming to evolve human-interpretable functions. [Citation Graph (0, 0)][DBLP]
    GECCO, 2006, pp:855-862 [Conf]
  48. Georges G. E. Gielen
    Future trends for wireless communication frontends in nanometer CMOS. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:600-605 [Conf]
  49. Jan Crols, Stéphane Donnay, Michiel Steyaert, Georges G. E. Gielen
    A high-level design and optimization tool for analog RF receiver front-ends. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:550-553 [Conf]
  50. Walter Daems, Georges G. E. Gielen, Willy M. C. Sansen
    Simulation-Based Automatic Generation of Signomial and Posynomial Performance Models for Analog Integrated Circuit Sizing. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:70-74 [Conf]
  51. Geert Debyser, Georges G. E. Gielen
    Efficient analog circuit synthesis with simultaneous yield and robustness optimization. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:308-311 [Conf]
  52. Kenneth Francken, Peter J. Vancorenland, Georges G. E. Gielen
    DAISY: A Simulation-Based High-Level Synthesis Tool for Delta-Sigma Modulators. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:188-192 [Conf]
  53. Kenneth Francken, Martin Vogels, Ewout Martens, Georges G. E. Gielen
    A behavioral simulation tool for continuous-time delta sigma modulators. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:234-239 [Conf]
  54. Georges G. E. Gielen, Zhihua Wang, Willy M. C. Sansen
    Fault detection and input stimulus determination for the testing of analog integrated circuits based on power-supply current monitoring. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:495-498 [Conf]
  55. Erik Lauwers, Georges G. E. Gielen
    ACTIF: A High-Level Power Estimation Tool for Analog Continuous-Time-Filters. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:193-196 [Conf]
  56. Domine Leenaerts, Rob A. Rutenbar, Georges G. E. Gielen
    Embedded Tutorial: CAD Solutions and Outstanding Challenges for Mixed-Signal and RF IC Design. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:- [Conf]
  57. Francky Leyn, Walter Daems, Georges G. E. Gielen, Willy M. C. Sansen
    A behavioral signal path modeling methodology for qualitative insight in and efficient sizing of CMOS opamps. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:374-381 [Conf]
  58. Francky Leyn, Georges G. E. Gielen, Willy M. C. Sansen
    An efficient DC root solving algorithm with guaranteed convergence for analog integrated CMOS circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:304-307 [Conf]
  59. Edward W. Y. Liu, Alberto L. Sangiovanni-Vincentelli, Georges G. E. Gielen, Paul R. Gray
    A Behavioral Representation for Nyquist Rate A/D Converters. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:386-389 [Conf]
  60. Piet Vanassche, Georges G. E. Gielen, Willy M. C. Sansen
    On the difference between two widely publicized methods for analyzing oscillator phase behavior. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:229-233 [Conf]
  61. Piet Vanassche, Georges G. E. Gielen, Willy M. C. Sansen
    A Generalized Method for Computing Oscillator Phase Noise Spectra. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:247-250 [Conf]
  62. Peter J. Vancorenland, Geert Van der Plas, Michiel Steyaert, Georges G. E. Gielen, Willy M. C. Sansen
    A Layout-Aware Synthesis Methodology for RF Circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:358-0 [Conf]
  63. Trent McConaghy, Georges G. E. Gielen
    Automation in mixed-signal design: challenges and solutions in the wake of the nano era. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:461-463 [Conf]
  64. Tao Chen, Georges G. E. Gielen
    Analysis of the dynamic SFDR property of high-accuracy current-steering D/A converters. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:973-976 [Conf]
  65. Tao Chen, Georges G. E. Gielen
    Modelling of the impact of the current source output impedance on the SFDR of current-steering CMOS D/A converters. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2004, pp:293-296 [Conf]
  66. Francisco V. Fernández, Georges G. E. Gielen, Lawrence Huelsman, Agnieszka Konczykowska, Stefano Manetti, Willy M. C. Sansen, Jiri Vlach
    Pleasures, Perils and Pitfalls of Symbolic Analysis. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:451-457 [Conf]
  67. Francisco V. Fernández, Piet Wambacq, Georges G. E. Gielen, Ángel Rodríguez-Vázquez, Willy M. C. Sansen
    Symbolic Analysis of Large Analog Integrated Circuits by Approximation During Expression Generation. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:25-28 [Conf]
  68. Georges G. E. Gielen, Geert Debyser, Piet Wambacq, Koen Swings, Willy M. C. Sansen
    Use of Symbolic Analysis in Analog Circuit Synthesis. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:2205-2208 [Conf]
  69. Georges G. E. Gielen, Willy M. C. Sansen
    Modeling of the Power-supply Interactions of CMOS Operational Amplifiers Using Symbolic Computation. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1381-1384 [Conf]
  70. Trent McConaghy, Georges G. E. Gielen
    Analysis of simulation-driven numerical performance modeling techniques for application to analog circuit optimization. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:1298-1301 [Conf]
  71. Trent McConaghy, Georges G. E. Gielen
    IBMG: interpretable behavioral model generator for nonlinear analog circuits via canonical form functions and genetic programming. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5170-5173 [Conf]
  72. Ewout Martens, Georges G. E. Gielen
    Behavioral modeling and simulation of weakly nonlinear sampled-data systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2247-2250 [Conf]
  73. João Ramos, Kenneth Francken, Georges G. E. Gielen, Michiel Steyaert
    Knowledge- and optimization-based design of RF power amplifiers. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2004, pp:629-632 [Conf]
  74. Zhihua Wang, Georges G. E. Gielen, Willy M. C. Sansen
    A Novel Method for the Fault Detection of Analog Integrated Circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:347-350 [Conf]
  75. Kenneth Francken, Georges G. E. Gielen
    Methodology for analog technology porting including performance tuning. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 1999, pp:415-418 [Conf]
  76. Martin Vogels, Kenneth Francken, Ewout Martens, Georges G. E. Gielen
    Efficient time-domain simulation of continuous-time Delta-Sigma A/D converters using analytical integration. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:237-240 [Conf]
  77. Francky Leyn, Erik Lauwers, Martin Vogels, Georges G. E. Gielen, Willy M. C. Sansen
    Regression criteria and their application in different modeling cases. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:85-8 [Conf]
  78. Minghu Jiang, Georges G. E. Gielen
    Backpropagation Analysis of the Limited Precision on High-Order Function Neural Networks. [Citation Graph (0, 0)][DBLP]
    ISNN (1), 2004, pp:305-310 [Conf]
  79. Minghu Jiang, Dafan Liu, Beixing Deng, Georges G. E. Gielen
    A Bayesian Classifier by Using the Adaptive Construct Algorithm of the RBF Networks. [Citation Graph (0, 0)][DBLP]
    ISNN (1), 2004, pp:876-881 [Conf]
  80. Didier Van Reeth, Georges G. E. Gielen
    A CAD Platform for Sensor Interfaces in Low-Power Applications. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:374-381 [Conf]
  81. Wim Verhaegen, Geert Van der Plas, Georges G. E. Gielen
    Automated test pattern generation for analog integrated circuits. [Citation Graph (0, 0)][DBLP]
    VTS, 1997, pp:296-301 [Conf]
  82. Minghu Jiang, Georges G. E. Gielen, Bo Zhang, Zhensheng Luo
    Fast Learning Algorithms for Feedforward Neural Networks. [Citation Graph (0, 0)][DBLP]
    Appl. Intell., 2003, v:18, n:1, pp:37-54 [Journal]
  83. Minghu Jiang, Georges G. E. Gielen
    The Effects of Quantization on Multi-Layer Feedforward Neural Networks. [Citation Graph (0, 0)][DBLP]
    IJPRAI, 2003, v:17, n:4, pp:637-661 [Journal]
  84. Minghu Jiang, Xiaoyan Zhu, Georges G. E. Gielen, Elliott Drábek, Ying Xia, Gang Tan, Ta Bao
    Braille to print translations for Chinese. [Citation Graph (0, 0)][DBLP]
    Information & Software Technology, 2002, v:44, n:2, pp:91-100 [Journal]
  85. Georges G. E. Gielen
    Editorial. [Citation Graph (0, 0)][DBLP]
    Integration, 2002, v:33, n:1-2, pp:1-2 [Journal]
  86. Minghu Jiang, Georges G. E. Gielen, Beixing Deng, Xiaoyan Zhu
    A fast learning algorithm for time-delay neural networks. [Citation Graph (0, 0)][DBLP]
    Inf. Sci., 2002, v:148, n:1-4, pp:27-39 [Journal]
  87. Mustafa Badaroglu, Kris Tiri, Geert Van der Plas, Piet Wambacq, Ingrid Verbauwhede, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man
    Clock-skew-optimization methodology for substrate-noise reduction with supply-current folding. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:6, pp:1146-1154 [Journal]
  88. Mustafa Badaroglu, Piet Wambacq, Geert Van der Plas, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man
    Digital ground bounce reduction by supply current shaping and clock frequency Modulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:1, pp:65-76 [Journal]
  89. Walter Daems, Georges G. E. Gielen, Willy M. C. Sansen
    Circuit simplification for the symbolic analysis of analogintegrated circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:4, pp:395-407 [Journal]
  90. Walter Daems, Georges G. E. Gielen, Willy M. C. Sansen
    Simulation-based generation of posynomial performance models for the sizing of analog integrated circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:5, pp:517-534 [Journal]
  91. Kenneth Francken, Georges G. E. Gielen
    A high-level simulation and synthesis environment for /spl Delta//spl Sigma/ modulators. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:8, pp:1049-1061 [Journal]
  92. Georges G. E. Gielen, Kenneth Francken, Ewout Martens, Martin Vogels
    An analytical integration method for the simulation of continuous-time /spl Delta//spl Sigma/ modulators. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:3, pp:389-399 [Journal]
  93. H. Alan Mantooth, Georges G. E. Gielen
    Guest editorial. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:2, pp:121-123 [Journal]
  94. E. S. J. Martens, Georges G. E. Gielen
    Analyzing continuous-time /spl Delta//spl Sigma/ Modulators with generic behavioral models. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:5, pp:924-932 [Journal]
  95. Geert Van der Plas, Geert Debyser, Francky Leyn, Koen Lampaert, Jan Vandenbussche, Georges G. E. Gielen, Willy M. C. Sansen, Petar Veselinovic, Domine Leenaerts
    AMGIE-A synthesis environment for CMOS analog integrated circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:9, pp:1037-1058 [Journal]
  96. Geert Van der Plas, Jan Vandenbussche, Georges G. E. Gielen, Willy M. C. Sansen
    A layout synthesis methodology for array-type analog blocks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:6, pp:645-661 [Journal]
  97. Carl De Ranter, Geert Van der Plas, Michiel Steyaert, Georges G. E. Gielen, Willy M. C. Sansen
    CYCLONE: automated design and layout of RF LC-oscillators. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:10, pp:1161-1170 [Journal]
  98. Bart De Smedt, Georges G. E. Gielen
    WATSON: design space boundary exploration and model generation for analog and RFIC design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:2, pp:213-224 [Journal]
  99. Piet Vanassche, Georges G. E. Gielen, Willy M. C. Sansen
    Symbolic modeling of periodically time-varying systems usingharmonic transfer matrices. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:9, pp:1011-1024 [Journal]
  100. Piet Vanassche, Georges G. E. Gielen, Willy M. C. Sansen
    Behavioral modeling of (coupled) harmonic oscillators. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:8, pp:1017-1026 [Journal]
  101. Zhihua Wang, Georges G. E. Gielen, Willy M. C. Sansen
    Probabilistic fault detection and the selection of measurements for analog integrated circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:9, pp:862-872 [Journal]
  102. Mustafa Badaroglu, Geert Van der Plas, Piet Wambacq, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man
    SWAN: high-level simulation methodology for digital substrate noise generation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:1, pp:23-33 [Journal]
  103. Trent McConaghy, Pieter Palmers, Georges G. E. Gielen, Michiel Steyaert
    Simultaneous Multi-Topology Multi-Objective Sizing Across Thousands of Analog Circuit Topologies. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:944-947 [Conf]
  104. Tom Eeckelaert, Raf Schoofs, Georges G. E. Gielen, Michiel Steyaert, Willy M. C. Sansen
    An efficient methodology for hierarchical synthesis of mixed-signal systems with fully integrated building block topology selection. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:81-86 [Conf]
  105. Mustafa Badaroglu, Geert Van der Plas, Piet Wambacq, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man
    Scalable Gate-Level Models for Power and Timing Analysis. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2938-2941 [Conf]
  106. E. Martens, G. Gielen
    A behavioral model of sampled-data systems in the phase-frequency transfer domain for architectural exploration of transceivers. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  107. Alkis A. Hatzopoulos, Stefanos Stefanou, Georges G. E. Gielen, Dominique Schreurs
    Assessment of parameter extraction methods for integrated inductor design and model validation. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  108. Trent McConaghy, Tom Eeckelaert, Georges G. E. Gielen
    CAFFEINE: Template-Free Symbolic Model Generation of Analog Circuits via Canonical Form Functions and Genetic Programming [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  109. Georges G. E. Gielen, Wim Dehaene, Phillip Christie, Dieter Draxelmayr, Edmond Janssens, Karen Maex, Ted Vucurevich
    Analog and Digital Circuit Design in 65 nm CMOS: End of the Road? [Citation Graph (0, 0)][DBLP]
    CoRR, 2007, v:0, n:, pp:- [Journal]
  110. Erik Lauwers, Georges G. E. Gielen
    Power estimation methods for analog circuits for architectural exploration of integrated systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:2, pp:155-162 [Journal]

  111. Design tool solutions for mixed-signal/RF circuit design in CMOS nanometer technologies. [Citation Graph (, )][DBLP]


  112. Guess, solder, measure, repeat: how do I get my mixed-signal chip right? [Citation Graph (, )][DBLP]


  113. From Transistor to PLL - Analogue Design and EDA Methods. [Citation Graph (, )][DBLP]


  114. High-level synthesis of analog sensor interface front-ends. [Citation Graph (, )][DBLP]


  115. Emerging Yield and Reliability Challenges in Nanometer CMOS Technologies. [Citation Graph (, )][DBLP]


  116. Massively multi-topology sizing of analog integrated circuits. [Citation Graph (, )][DBLP]


  117. A design methodology for fully reconfigurable Delta-Sigma data converters. [Citation Graph (, )][DBLP]


  118. Efficient reliability simulation of analog ICs including variability and time-varying stress. [Citation Graph (, )][DBLP]


  119. Health-care electronics The market, the challenges, the progress. [Citation Graph (, )][DBLP]


  120. Variability-aware reliability simulation of mixed-signal ICs with quasi-linear complexity. [Citation Graph (, )][DBLP]


  121. An accurate and efficient yield optimization method for analog circuits based on computing budget allocation and memetic search technique. [Citation Graph (, )][DBLP]


  122. Design tools and circuit solutions for degradation-resilient analog circuits in nanometer CMOS. [Citation Graph (, )][DBLP]


  123. An intelligent design system for analogue integrated circuits. [Citation Graph (, )][DBLP]


  124. Importance sampled circuit learning ensembles for robust analog IC design. [Citation Graph (, )][DBLP]


  125. Automated extraction of expert knowledge in analog topology selection and sizing. [Citation Graph (, )][DBLP]


  126. ISCLEs: Importance Sampled Circuit Learning Ensembles for Trustworthy Analog Circuit Topology Synthesis. [Citation Graph (, )][DBLP]


  127. A methodology for measuring transistor ageing effects towards accurate reliability simulation. [Citation Graph (, )][DBLP]


  128. A low-power mixing DAC IR-UWB-receiver. [Citation Graph (, )][DBLP]


  129. Fuzzy selection based differential evolution algorithm for analog cell sizing capturing imprecise human intentions. [Citation Graph (, )][DBLP]


  130. Generic Behavioral Modeling of Analog and Mixed-Signal Systems. [Citation Graph (, )][DBLP]


  131. High-Level Design Case of a Switched-Capacitor Low-Pass Filter Using Verilog-A. [Citation Graph (, )][DBLP]


  132. Modeling and Simulation of a Sigma-Delta Digital to Analog Converter Using VHDL-AMS. [Citation Graph (, )][DBLP]


  133. Analysis of quantization effects on high-order function neural networks. [Citation Graph (, )][DBLP]


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