The SCEAS System
Navigation Menu
Introduction
Collection Based
Clustering
Ranking
Paper Based
Journals
Conferences
DB Status
Statistics
Search

Search the dblp DataBase

Title:
Author:
Hideo Fujiwara: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Masahide Miyazaki, Tomokazu Yoneda, Hideo Fujiwara
    A memory grouping method for sharing memory BIST logic. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:671-676 [Conf]
  2. Satoshi Ohtake, Shintaro Nagai, Hiroki Wada, Hideo Fujiwara
    A DFT method for RTL circuits to achieve complete fault efficiency based on fixed-control testability. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:331-334 [Conf]
  3. Satoshi Ohtake, Hiroki Wada, Toshimitsu Masuzawa, Hideo Fujiwara
    A non-scan DFT method at register-transfer level to achieve complete fault efficiency. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:599-604 [Conf]
  4. Tomoya Takasaki, Tomoo Inoue, Hideo Fujiwara
    Partial Scan Design Methods Based on Internally Balanced Structure. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 1998, pp:211-216 [Conf]
  5. Md. Altaf-Ul-Amin, Satoshi Ohtake, Hideo Fujiwara
    Design for Hierarchical Two-Pattern Testability of Data Paths. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2001, pp:11-16 [Conf]
  6. Atlaf Ul Amin, Satoshi Ohtake, Hideo Fujiwara
    Design for Two-Pattern Testability of Controller-Data Path Circuits. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2002, pp:73-79 [Conf]
  7. Thomas Clouqueur, Hideo Fujiwara, Kewal K. Saluja
    A Class of Linear Space Compactors for Enhanced Diagnostic. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2005, pp:260-265 [Conf]
  8. Debesh Kumar Das, Tomoo Inoue, Susanta Chakraborty, Hideo Fujiwara
    Max-Testable Class of Sequential Circuits having Combinational Test Generation Complexity. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2004, pp:342-347 [Conf]
  9. Debesh Kumar Das, Satoshi Ohtake, Hideo Fujiwara
    New DFT Techniques of Non-Scan Sequential Circuits with Complete Fault Efficiency. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1999, pp:263-268 [Conf]
  10. Emil Gizdarski, Hideo Fujiwara
    Spirit: satisfiability problem implementation for redundancy identification and test generation. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2000, pp:171-178 [Conf]
  11. Emil Gizdarski, Hideo Fujiwara
    Fault Set Partition for Efficient Width Compression. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2002, pp:194-199 [Conf]
  12. Toshinori Hosokawa, Hiroshi Date, Masahide Miyazaki, Michiaki Muraoka, Hideo Fujiwara
    A Method of Test Plan Grouping to Shorten Test Length for RTL Data Paths under a Test Controller Area Constraint. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:130-135 [Conf]
  13. Toshinori Hosokawa, Toshihiro Hiraoka, Tomoo Inoue, Hideo Fujiwara
    Static and Dynamic Test Sequence Compaction Methods for Acyclic Sequential Circuits Using a Time Expansion Model. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1999, pp:192-0 [Conf]
  14. Hideyuki Ichihara, Tomoo Inoue, Naoki Okamoto, Toshinori Hosokawa, Hideo Fujiwara
    An Effective Design for Hierarchical Test Generation Based on Strong Testability. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2005, pp:288-293 [Conf]
  15. Tomoo Inoue, Hideo Fujiwara, Hiroyuki Michinishi, Tokumi Yokohira, Takuji Okamoto
    Universal test complexity of field-programmable gate arrays. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1995, pp:259-265 [Conf]
  16. Michiko Inoue, Emil Gizdarski, Hideo Fujiwara
    A class of sequential circuits with combinational test generation complexity under single-fault assumption. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2000, pp:398-403 [Conf]
  17. Tomoo Inoue, Toshinori Hosokawa, Takahiro Mihara, Hideo Fujiwara
    An Optimal Time Expansion Model Based on Combinational ATPG for RT level Circuits. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1998, pp:190-197 [Conf]
  18. Michiko Inoue, Takeshi Higashimura, Kenji Noda, Toshimitsu Masuzawa, Hideo Fujiwara
    A High-Level Synthesis Method for Weakly Testable Data Paths. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1998, pp:40-45 [Conf]
  19. Tomoo Inoue, Satoshi Miyazaki, Hideo Fujiwara
    On the Complexity of Universal Fault Diagnosis for Look-up Table FPGAs. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1997, pp:276-281 [Conf]
  20. Tomoo Inoue, Tomokazu Miura, Akio Tamura, Hideo Fujiwara
    A Scheduling Method in High-Level Synthesis for Acyclic Partial Scan Design. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2002, pp:128-133 [Conf]
  21. Tomoo Inoue, Toshimitsu Masuzawa, Hiroshi Youra, Hideo Fujiwara
    An Approach To The Synthesis Of Synchronizable Finite State Machines With Partial Scan. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1996, pp:130-135 [Conf]
  22. Michiko Inoue, Kazuhiro Suzuki, Hiroyuki Okamoto, Hideo Fujiwara
    Test Synthesis for Datapaths Using Datapath-Controller Functions. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:294-299 [Conf]
  23. Tsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara
    Reducibility of Sequential Test Generation to Combinational Test Generation for Several Delay Fault Models. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:58-63 [Conf]
  24. Hiroyuki Iwata, Tomokazu Yoneda, Satoshi Ohtake, Hideo Fujiwara
    A DFT Method for RTL Data Paths Based on Partially Strong Testability to Guarantee Complete Fault Efficiency. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2005, pp:306-311 [Conf]
  25. Kazuko Kambe, Michiko Inoue, Hideo Fujiwara
    Efficient Template Generation for Instruction-Based Self-Test of Processor Cores. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2004, pp:152-157 [Conf]
  26. Kazuko Kambe, Michiko Inoue, Hideo Fujiwara, Tsuyoshi Iwagaki
    Efficient Constraint Extraction for Template-Based Processor Self-Test Generation. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2005, pp:444-449 [Conf]
  27. Erik Larsson, Klas Arvidsson, Hideo Fujiwara, Zebo Peng
    Integrated Test Scheduling, Test Parallelization and TAMDesign. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2002, pp:397-404 [Conf]
  28. Erik Larsson, Hideo Fujiwara
    Optimal System-on-Chip Test Scheduling. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:306-311 [Conf]
  29. Xiaowei Li, Toshimitsu Masuzawa, Hideo Fujiwara
    Strong self-testability for data paths high-level synthesis. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2000, pp:229-234 [Conf]
  30. Toshimitsu Masuzawa, Minoru Izutsu, Hiroki Wada, Hideo Fujiwara
    Single-control testability of RTL data paths for BIST. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2000, pp:210-215 [Conf]
  31. Hiroyuki Michinishi, Tokumi Yokohira, Takuji Okamoto, Tomoo Inoue, Hideo Fujiwara
    A Test Methodology for Interconnect Structures of LUT-based FPGAs. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1996, pp:68-74 [Conf]
  32. Hiroyuki Michinishi, Tokumi Yokohira, Takuji Okamoto, Tomoo Inoue, Hideo Fujiwara
    Testing for the programming circuit of LUT-based FPGAs. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1997, pp:242-247 [Conf]
  33. Masahide Miyazaki, Toshinori Hosokawa, Hiroshi Date, Michiaki Muraoka, Hideo Fujiwara
    A DFT Selection Method for Reducing Test Application Time of System-on-Chips. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:412-417 [Conf]
  34. Satoshi Ohtake, Tomoo Inoue, Hideo Fujiwara
    Sequential Test Generation Based on Circuit Pseudo-Transformation. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1997, pp:62-67 [Conf]
  35. Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara
    A Method of Test Generation for Weakly Testable Data Paths Using Test Knowledge Extracted from RTL Description. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1999, pp:5-12 [Conf]
  36. Satoshi Ohtake, Toshimitsu Masuzawa, Hideo Fujiwara
    A Non-Scan DFT Method for Controllers to Achieve Complete Fault Efficiency. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1998, pp:204-211 [Conf]
  37. Chia Yee Ooi, Hideo Fujiwara
    Classification of Sequential Circuits Based on ?k Notation. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2004, pp:348-353 [Conf]
  38. Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara
    Software-Based Delay Fault Testing of Processor Cores. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:68-71 [Conf]
  39. Tomoya Takasaki, Hideo Fujiwara, Tomoo Inoue
    A High-Level Synthesis Approach to Partial Scan Design Based on Acyclic Structure. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 1999, pp:309-314 [Conf]
  40. Dong Xiang, Ming-Jing Chen, Hideo Fujiwara
    Using Weighted Scan Enable Signals to Improve the Effectiveness of Scan-Based BIST. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2005, pp:126-131 [Conf]
  41. Dong Xiang, Ming-Jing Chen, Jia-Guang Sun, Hideo Fujiwara
    Improving Test Quality of Scan-Based BIST by Scan Chain Partitioning. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:12-17 [Conf]
  42. Dong Xiang, Shan Gu, Hideo Fujiwara
    Non-Scan Design for Testability Based on Fault Oriented Conflict Analysis. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2002, pp:86-0 [Conf]
  43. Dong Xiang, Shan Gu, Hideo Fujiwara
    Non-Scan Design for Testability for Mixed RTL Circuits with Both Data Paths and Controller via Conflict Analysis. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2003, pp:300-305 [Conf]
  44. Dong Xiang, Kai-Wei Li, Hideo Fujiwara
    Design for Cost Effective Scan Testing by Reconfiguring Scan Flip-Flops. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2005, pp:318-323 [Conf]
  45. Ken-ichi Yamaguchi, Hiroki Wada, Toshimitsu Masuzawa, Hideo Fujiwara
    BIST Method Based on Concurrent Single-Control Testability of RTL Data Paths. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2001, pp:313-318 [Conf]
  46. Tomokazu Yoneda, Hideo Fujiwara
    A DFT Method for Core-Based Systems-on-a-Chip Based on Consecutive Testability. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2001, pp:193-198 [Conf]
  47. Tomokazu Yoneda, Hisakazu Takakuwa, Hideo Fujiwara
    Power-Constrained Area and Time Co-Optimization for SoCs Based on Consecutive Testability. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2005, pp:150-155 [Conf]
  48. Yuki Yoshikaw, Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara
    Design for Testability Based on Single-Port-Change Delay Testing for Data Paths. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2005, pp:254-259 [Conf]
  49. Zhiqiang You, Ken-ichi Yamaguchi, Michiko Inoue, Jacob Savir, Hideo Fujiwara
    Power-Constrained DFT Algorithms for Non-Scan BIST-able RTL Data Paths. [Citation Graph (0, 0)][DBLP]
    Asian Test Symposium, 2004, pp:32-39 [Conf]
  50. Emil Gizdarski, Hideo Fujiwara
    A Framework for Low Complexity Static Learning. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:546-549 [Conf]
  51. Satoshi Ohtake, Kouhei Ohtani, Hideo Fujiwara
    A Method of Test Generation fo Path Delay Faults Using Stuck-at Fault Test Generation Algorithms. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10310-10315 [Conf]
  52. Ilia Polian, Hideo Fujiwara
    Functional constraints vs. test compression in scan-based delay testing. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1039-1044 [Conf]
  53. Tomokazu Yoneda, Kimihiko Masuda, Hideo Fujiwara
    Power-constrained test scheduling for multi-clock domain SoCs. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:297-302 [Conf]
  54. Mariane Comte, Satoshi Ohtake, Hideo Fujiwara, Michel Renovell
    Electrical Behavior of GOS Fault affected Domino Logic Cell. [Citation Graph (0, 0)][DBLP]
    DELTA, 2006, pp:183-189 [Conf]
  55. Ilia Polian, Bernd Becker, Masato Nakasato, Satoshi Ohtake, Hideo Fujiwara
    Low-Cost Hardening of Image Processing Applications Against Soft Errors. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:274-279 [Conf]
  56. Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara
    Testing Superscalar Processors in Functional Mode. [Citation Graph (0, 0)][DBLP]
    FPL, 2005, pp:747-750 [Conf]
  57. Takayuli Fujino, Hideo Fujiwara
    An Efficient Test Generation Algorithm Based on Search State Dominance. [Citation Graph (0, 0)][DBLP]
    FTCS, 1992, pp:246-253 [Conf]
  58. Kunihiko Hayashi, Michiko Inoue, Toshimitsu Masuzawa, Hideo Fujiwara
    A Layout Adjustment Problem for Disjoint Rectangles Preserving Orthogonal Order. [Citation Graph (0, 0)][DBLP]
    Graph Drawing, 1998, pp:183-197 [Conf]
  59. Tomoo Inoue, Debesh Kumar Das, Chiiho Sano, Takahiro Mihara, Hideo Fujiwara
    Test Generation for Acyclic Sequential Circuits with Hold Registers. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:550-556 [Conf]
  60. Michiko Inoue, Chikateru Jinno, Hideo Fujiwara
    An Extended Class of Sequential Circuits with Combinational Test Generation Complexity. [Citation Graph (0, 0)][DBLP]
    ICCD, 2002, pp:200-205 [Conf]
  61. Yasuro Sato, Michiko Inoue, Toshimitsu Masuzawa, Hideo Fujiwara
    A Snapshot Algorithm for Distributed Mobile Systems. [Citation Graph (0, 0)][DBLP]
    ICDCS, 1996, pp:734-743 [Conf]
  62. Akihiro Fujiwara, Michiko Inoue, Toshimitsu Masuzawa, Hideo Fujiwara
    A Parallel Algorithm for Weighted Distance Transforms. [Citation Graph (0, 0)][DBLP]
    IPPS, 1997, pp:407-412 [Conf]
  63. Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara
    Instruction-based delay fault self-testing of pipelined processor cores. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 2005, pp:5686-5689 [Conf]
  64. Takashi Ishimizu, Akihiro Fujiwara, Michiko Inoue, Toshimitsu Masuzawa, Hideo Fujiwara
    Parallel Algorithms for All Nearest Neighbors of Binary Images on the BSP Model. [Citation Graph (0, 0)][DBLP]
    ISPAN, 1999, pp:394-399 [Conf]
  65. Hideo Fujiwara, Osamu Fujisawa, Kazunori Hikone
    Enhancing Random-Pattern Coverage of Programmable Logic Arrays via Masking Technique. [Citation Graph (0, 0)][DBLP]
    ITC, 1988, pp:642-648 [Conf]
  66. Hideo Fujiwara, Kewal K. Saluja, Kozo Kinoshita
    A Testable Design of Programmable Logic Arrays with Universal Control and Minimal Overhead. [Citation Graph (0, 0)][DBLP]
    ITC, 1985, pp:574-582 [Conf]
  67. Hideo Fujiwara, Akihiro Yamamoto
    Parity-Scan Design to Reduce the Cost of Test Application. [Citation Graph (0, 0)][DBLP]
    ITC, 1992, pp:283-292 [Conf]
  68. Dong Xiang, Yi Xu, Hideo Fujiwara
    Non-scan design for testability for synchronous sequential circuits based on conflict analysis. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:520-529 [Conf]
  69. Tomokazu Yoneda, Tetsuo Uchiyama, Hideo Fujiwara
    Area and Time Co-Optimization for System-on-a-Chip based on Consecutive Testability. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:415-422 [Conf]
  70. Sen Moriya, Michiko Inoue, Toshimitsu Masuzawa, Hideo Fujiwara
    SelfStabilizing WaitFree Clock Synchronization with Bounded Space. [Citation Graph (0, 0)][DBLP]
    OPODIS, 1998, pp:129-144 [Conf]
  71. Debesh Kumar Das, Bhargab B. Bhattacharya, Satoshi Ohtake, Hideo Fujiwara
    Testable Design of Sequential Circuits with Improved Fault Efficiency. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:128-133 [Conf]
  72. Hideo Fujiwara
    A New Definition and a New Class of Sequential Circuits with Combinational Test Generation Complexity. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:288-293 [Conf]
  73. Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara
    Instruction-Based Delay Fault Self-Testing of Processor Cores. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:933-0 [Conf]
  74. Hiroki Wada, Toshimitsu Masuzawa, Kewal K. Saluja, Hideo Fujiwara
    Design for Strong Testability of RTL Data Paths to Provide Complete Fault Efficiency. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:300-305 [Conf]
  75. Emil Gizdarski, Hideo Fujiwara
    SPIRIT: A Highly Robust Combinational Test Generation Algorithm. [Citation Graph (0, 0)][DBLP]
    VTS, 2001, pp:346-351 [Conf]
  76. Tomoo Inoue, Hironori Maeda, Hideo Fujiwara
    A scheduling problem in test generation. [Citation Graph (0, 0)][DBLP]
    VTS, 1995, pp:344-349 [Conf]
  77. Erik Larsson, Hideo Fujiwara
    Test Resource Partitioning and Optimization for SOC Designs. [Citation Graph (0, 0)][DBLP]
    VTS, 2003, pp:319-324 [Conf]
  78. Satoshi Ohtake, Hideo Fujiwara, Shunjiro Miwa
    A Method of Test Generation for Path Delay Faults in Balanced Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    VTS, 2002, pp:321-327 [Conf]
  79. Yoshiyuki Nakamura, Jacob Savir, Hideo Fujiwara
    BIST Pretest of ICs: Risks and Benefits. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:142-149 [Conf]
  80. Tomokazu Yoneda, Hideo Fujiwara
    Design for Consecutive Transparency of Cores in System-on-a-Chip. [Citation Graph (0, 0)][DBLP]
    VTS, 2003, pp:287-292 [Conf]
  81. Tomokazu Yoneda, Akiko Shuto, Hideyuki Ichihara, Tomoo Inoue, Hideo Fujiwara
    TAM Design and Optimization for Transparency-Based SoC Test. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:381-388 [Conf]
  82. Thomas Edison Yu, Tomokazu Yoneda, Danella Zhao, Hideo Fujiwara
    Using Domain Partitioning in Wrapper Design for IP Cores Under Power Constraints. [Citation Graph (0, 0)][DBLP]
    VTS, 2007, pp:369-374 [Conf]
  83. Michiko Inoue, Sen Moriya, Toshimitsu Masuzawa, Hideo Fujiwara
    Optimal Wait-Free Clock Synchronisation Protocol on a Shared-Memory Multi-processor System. [Citation Graph (0, 0)][DBLP]
    WDAG, 1997, pp:290-304 [Conf]
  84. Michiko Inoue, Shinya Umetani, Toshimitsu Masuzawa, Hideo Fujiwara
    Adaptive Long-Lived O(k2)-Renaming with O(k2) Steps. [Citation Graph (0, 0)][DBLP]
    DISC, 2001, pp:123-135 [Conf]
  85. Eiichiro Ueda, Yoshiaki Katayama, Toshimitsu Masuzawa, Hideo Fujiwara
    A latency-optimal superstabilizing mutual exclusion protocol. [Citation Graph (0, 0)][DBLP]
    WSS, 1997, pp:110-124 [Conf]
  86. Debesh K. Das, Hideo Fujiwara, Yungang Li, Yinghua Min, Shiyi Xu, Yervant Zorian
    Design & Test Education in Asia. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2004, v:21, n:4, pp:331-338 [Journal]
  87. Hideo Fujiwara
    Needed: Third-generation ATPG Benchmarks. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1998, v:15, n:1, pp:96-0 [Journal]
  88. Tomoo Inoue, Satoshi Miyazaki, Hideo Fujiwara
    Universal Fault Diagnosis for Lookup Table FPGAs. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1998, v:15, n:1, pp:39-44 [Journal]
  89. Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara
    Delay Fault Testing of Processor Cores in Functional Mode. [Citation Graph (0, 0)][DBLP]
    IEICE Transactions, 2005, v:88, n:3, pp:610-618 [Journal]
  90. Michiko Inoue, Hideo Fujiwara
    An approach to test synthesis from higher level. [Citation Graph (0, 0)][DBLP]
    Integration, 1998, v:26, n:1-2, pp:101-116 [Journal]
  91. Akihiro Fujiwara, Toshimitsu Masuzawa, Hideo Fujiwara
    An Optimal Parallel Algorithm for the Euclidean Distance Maps of 2-D Binary Images. [Citation Graph (0, 0)][DBLP]
    Inf. Process. Lett., 1995, v:54, n:5, pp:295-300 [Journal]
  92. Yoshiaki Katayama, Eiichiro Ueda, Hideo Fujiwara, Toshimitsu Masuzawa
    A Latency Optimal Superstabilizing Mutual Exclusion Protocol in Unidirectional Rings. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 2002, v:62, n:5, pp:865-884 [Journal]
  93. Akihiro Fujiwara, Michiko Inoue, Toshimitsu Masuzawa, Hideo Fujiwara
    A cost optimal parallel algorithm for weighted distance transforms. [Citation Graph (0, 0)][DBLP]
    Parallel Computing, 1999, v:25, n:4, pp:405-416 [Journal]
  94. Hideo Fujiwara, Satoshi Ohtake, Tomoya Takasaki
    A sequential circuit structure with combinational test generation complexity and its application. [Citation Graph (0, 0)][DBLP]
    Systems and Computers in Japan, 1997, v:28, n:11, pp:11-21 [Journal]
  95. Kunihiko Hayashi, Michiko Inoue, Toshimitsu Masuzawa, Hideo Fujiwara
    A layout adjustment problem for disjoint rectangles preserving orthogonal order. [Citation Graph (0, 0)][DBLP]
    Systems and Computers in Japan, 2002, v:33, n:2, pp:31-42 [Journal]
  96. Akihiro Fujiwara, Toshimitsu Masuzawa, Hideo Fujiwara
    Parallel algorithms for connected-component problems of gray-scale images. [Citation Graph (0, 0)][DBLP]
    Systems and Computers in Japan, 1997, v:28, n:1, pp:74-86 [Journal]
  97. Toshinori Hosokawa, Tomoo Inoue, Toshihiro Hiraoka, Hideo Fujiwara
    Test sequence compaction methods for acyclic sequential circuits using a time expansion model. [Citation Graph (0, 0)][DBLP]
    Systems and Computers in Japan, 2002, v:33, n:10, pp:105-115 [Journal]
  98. Takashi Ishimizu, Akihiro Fujiwara, Michiko Inoue, Toshimitsu Masuzawa, Hideo Fujiwara
    Parallel algorithms for selection on the BSP and BSP* models. [Citation Graph (0, 0)][DBLP]
    Systems and Computers in Japan, 2002, v:33, n:12, pp:97-107 [Journal]
  99. Chikara Ohori, Michiko Inoue, Toshimitsu Masuzawa, Hideo Fujiwara
    A causal broadcast protocol for distributed mobile systems. [Citation Graph (0, 0)][DBLP]
    Systems and Computers in Japan, 2001, v:32, n:3, pp:65-75 [Journal]
  100. Satoshi Ohtake, Toshimitsu Masuzawa, Hideo Fujiwara
    A nonscan DFT method for controllers to provide complete fault efficiency. [Citation Graph (0, 0)][DBLP]
    Systems and Computers in Japan, 2002, v:33, n:5, pp:64-75 [Journal]
  101. Katsuyuki Takabatake, Michiko Inoue, Toshimitsu Masuzawa, Hideo Fujiwara
    Non-scan design for testable data paths using thru operation. [Citation Graph (0, 0)][DBLP]
    Systems and Computers in Japan, 1997, v:28, n:10, pp:60-68 [Journal]
  102. Tomoya Takasaki, Tomoo Inoue, Hideo Fujiwara
    Partial scan design methods based on internally balanced structure. [Citation Graph (0, 0)][DBLP]
    Systems and Computers in Japan, 1998, v:29, n:10, pp:26-35 [Journal]
  103. Daisuke Yoshida, Toshimitsu Masuzawa, Hideo Fujiwara
    Fault-tolerant distributed algorithms for autonomous mobile robots with crash faults. [Citation Graph (0, 0)][DBLP]
    Systems and Computers in Japan, 1997, v:28, n:2, pp:33-43 [Journal]
  104. Hiroshi Youra, Tomoo Inoue, Toshimitsu Masuzawa, Hideo Fujiwara
    On the synthesis of synchronizable finite state machines with partial scan. [Citation Graph (0, 0)][DBLP]
    Systems and Computers in Japan, 1998, v:29, n:1, pp:53-62 [Journal]
  105. Tomokazu Yoneda, Hideo Fujiwara
    Design for consecutive transparency method of RTL circuits. [Citation Graph (0, 0)][DBLP]
    Systems and Computers in Japan, 2006, v:37, n:2, pp:1-10 [Journal]
  106. Hideo Fujiwara
    A New Class of Sequential Circuits with Combinational Test Generation Complexity. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2000, v:49, n:9, pp:895-905 [Journal]
  107. Hideo Fujiwara
    On Closedness and Test Complexity of Logic Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1981, v:30, n:8, pp:556-562 [Journal]
  108. Hideo Fujiwara
    A New PLA Design for Universal Testability. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1984, v:33, n:8, pp:745-750 [Journal]
  109. Hideo Fujiwara
    Computational Complexity of Controllability/Observability Problems for Combinational Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1990, v:39, n:6, pp:762-767 [Journal]
  110. Hideo Fujiwara, Kozo Kinoshita
    On the Computational Complexity of System Diagnosis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1978, v:27, n:10, pp:881-885 [Journal]
  111. Hideo Fujiwara, Kozo Kinoshita
    Connection Assignments for Probabilistically Diagnosable Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1978, v:27, n:3, pp:280-283 [Journal]
  112. Hideo Fujiwara, Kozo Kinoshita
    Some Existence Theorems for Probabilistically Diagnosable Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1978, v:27, n:4, pp:379-384 [Journal]
  113. Hideo Fujiwara, Kozo Kinoshita
    A Design of Programmable Logic Arrays with Universal Tests. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1981, v:30, n:11, pp:823-828 [Journal]
  114. Hideo Fujiwara, Yoich Nagao, Tsutomu Sasao, Kozo Kinoshita
    Easily Testable Sequential Machines with Extra Inputs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1975, v:24, n:8, pp:821-826 [Journal]
  115. Hideo Fujiwara, Takeshi Shimono
    On the Acceleration of Test Generation Algorithms. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1983, v:32, n:12, pp:1137-1144 [Journal]
  116. Hideo Fujiwara, Shunichi Toida
    The Complexity of Fault Detection Problems for Combinational Logic Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1982, v:31, n:6, pp:555-560 [Journal]
  117. Kewal K. Saluja, Kozo Kinoshita, Hideo Fujiwara
    An Easily Testable Design of Programmable Logic Arrays for Multiple Faults. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1983, v:32, n:11, pp:1038-1046 [Journal]
  118. Robert P. Treuer, Vinod K. Agarwal, Hideo Fujiwara
    A New Built-In Self-Test Design for PLA's with High Fault Coverage and Low Overhead. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1987, v:36, n:3, pp:369-373 [Journal]
  119. Dong Xiang, Yi Xu, Hideo Fujiwara
    Nonscan Design for Testability for Synchronous Sequential Circuits Based on Conflict Resolution. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2003, v:52, n:8, pp:1063-1075 [Journal]
  120. Dong Xiang, Kaiwei Li, Jiaguang Sun, Hideo Fujiwara
    Reconfigured Scan Forest for Test Application Cost, Test Data Volume, and Test Power Reduction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2007, v:56, n:4, pp:557-562 [Journal]
  121. Hideo Fujiwara
    Enhancing random-pattern coverage of programmable logic arrays via masking technique. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:9, pp:1022-1025 [Journal]
  122. Hideo Fujiwara, Tomoo Inoue
    Optimal granularity of test generation in a distributed system. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:8, pp:885-892 [Journal]
  123. Hideo Fujiwara, Akihiro Yamamoto
    Parity-scan design to reduce the cost of test application. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:10, pp:1604-1611 [Journal]
  124. Emil Gizdarski, Hideo Fujiwara
    SPIRIT: a highly robust combinational test generation algorithm. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:12, pp:1446-1458 [Journal]
  125. Erik Larsson, Klas Arvidsson, Hideo Fujiwara, Zebo Peng
    Efficient test solutions for core-based designs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:5, pp:758-775 [Journal]
  126. Dong Xiang, Ming-Jing Chen, Jia-Guang Sun, Hideo Fujiwara
    Improving test effectiveness of scan-based BIST by scan chain partitioning. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:6, pp:916-927 [Journal]
  127. Dong Xiang, Hideo Fujiwara
    Handling the pin overhead problem of DFTs for high-quality and at-speed tests. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:9, pp:1105-1113 [Journal]
  128. Hideo Fujiwara, Tomoo Inoue
    Optimal Granularity and Scheme of Parallel Test Generation in a Distributed System. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1995, v:6, n:7, pp:677-686 [Journal]
  129. Erik Larsson, Hideo Fujiwara
    System-on-chip test scheduling with reconfigurable core wrappers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:3, pp:305-309 [Journal]
  130. Hiroyuki Iwata, Tomokazu Yoneda, Hideo Fujiwara
    A DFT Method for Time Expansion Model at Register Transfer Level. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:682-687 [Conf]
  131. Tomokazu Yoneda, Masahiro Imanishi, Hideo Fujiwara
    Interactive presentation: An SoC test scheduling algorithm using reconfigurable union wrappers. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:231-236 [Conf]
  132. Dan Zhao, Ronghua Huang, Tomokazu Yoneda, Hideo Fujiwara
    Power-Aware Multi-Frequency Heterogeneous SoC Test Framework Design with Floor-Ceiling Packing. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2942-2945 [Conf]
  133. Tsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara
    A New Test Generation Model for Broadside Transition Testing of Partial Scan Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI-SoC, 2006, pp:308-313 [Conf]
  134. Fawnizu Azmadi Hussin, Tomokazu Yoneda, Hideo Fujiwara
    Optimization of NoC Wrapper Design under Bandwidth and Test Time Constraints. [Citation Graph (0, 0)][DBLP]
    European Test Symposium, 2007, pp:35-42 [Conf]
  135. Dong Xiang, Mingjing Chen, Hideo Fujiwara
    Using Weighted Scan Enable Signals to Improve Test Effectiveness of Scan-Based BIST. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2007, v:56, n:12, pp:1619-1628 [Journal]
  136. Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara
    Instruction-Based Self-Testing of Delay Faults in Pipelined Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:11, pp:1203-1215 [Journal]
  137. Yoshiyuki Nakamura, Thomas Clouqueur, Kewal K. Saluja, Hideo Fujiwara
    Diagnosing At-Speed Scan BIST Circuits Using a Low Speed and Low Memory Tester. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:7, pp:790-800 [Journal]

  138. Fast false path identification based on functional unsensitizability using RTL information. [Citation Graph (, )][DBLP]


  139. Test infrastructure design for core-based system-on-chip under cycle-accurate thermal constraints. [Citation Graph (, )][DBLP]


  140. Localized random access scan: Towards low area and routing overhead. [Citation Graph (, )][DBLP]


  141. Shelf Packing to the Design and Optimization of A Power-Aware Multi-Frequency Wrapper Architecture for Modular IP Cores. [Citation Graph (, )][DBLP]


  142. Core-Based Testing of Multiprocessor System-on-Chips Utilizing Hierarchical Functional Buses. [Citation Graph (, )][DBLP]


  143. Wrapper and TAM Co-Optimization for Reuse of SoC Functional Interconnects. [Citation Graph (, )][DBLP]


  144. Enabling False Path Identification from RTL for Reducing Design and Test Futileness. [Citation Graph (, )][DBLP]


  145. Graph theoretic approach for scan cell reordering to minimize peak shift power. [Citation Graph (, )][DBLP]


  146. Efficient path delay test generation based on stuck-at test generation using checker circuitry. [Citation Graph (, )][DBLP]


  147. Generating Compact Robust and Non-Robust Tests for Complete Coverage of Path Delay Faults Based on Stuck-at Tests. [Citation Graph (, )][DBLP]


  148. Power-Constrained SOC Test Schedules through Utilization of Functional Buses. [Citation Graph (, )][DBLP]


  149. A New Class of Sequential Circuits with Acyclic Test Generation Complexity. [Citation Graph (, )][DBLP]


  150. On Minimization of Test Application Time for RAS. [Citation Graph (, )][DBLP]


  151. Brief Announcement: Acceleration by Contention for Shared Memory Mutual Exclusion Algorithms. [Citation Graph (, )][DBLP]


  152. Partial Scan Approach for Secret Information Protection. [Citation Graph (, )][DBLP]


  153. Scan cell reordering to minimize peak power during test cycle: A graph theoretic approach. [Citation Graph (, )][DBLP]


  154. Test pattern selection to optimize delay test quality with a limited size of test set. [Citation Graph (, )][DBLP]


Search in 0.007secs, Finished in 0.918secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
Introduction Collection Based Clustering Ranking Paper Based Journals Conferences DB Status Statistics Search
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002