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Ashok K. Murugavel: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Ashok K. Murugavel, N. Ranganathan
    A Real Delay Switching Activity Simulator based on Petri net Modeling. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:181-186 [Conf]
  2. N. Ranganathan, Ashok K. Murugavel
    A low power scheduler using game theory. [Citation Graph (0, 0)][DBLP]
    CODES+ISSS, 2003, pp:126-131 [Conf]
  3. Ashok K. Murugavel, N. Ranganathan
    Petri net modeling of gate and interconnect delays for power estimation. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:455-460 [Conf]
  4. N. Ranganathan, Ashok K. Murugavel
    A Microeconomic Model for Simultaneous Gate Sizing and Voltage Scaling for Power Optimization. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:276-281 [Conf]
  5. Ashok K. Murugavel, N. Ranganathan
    Power estimation of sequential circuits using hierarchical colored hardware petri net modeling. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2002, pp:267-270 [Conf]
  6. Ashok K. Murugavel, N. Ranganathan
    A Real Delay Switching Activity Simulator Based on Petri Net Modeling. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:181-186 [Conf]
  7. Ashok K. Murugavel, N. Ranganathan
    A Game-Theoretic Approach for Binding in Behavioral Synthesis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:452-0 [Conf]
  8. Ashok K. Murugavel, N. Ranganathan
    Gate Sizing and Buffer Insertion using Economic Models for Power Optimization. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:195-200 [Conf]
  9. Ashok K. Murugavel, N. Ranganathan
    Game Theoretic Modeling of Voltage and Frequency Scaling during Behavioral Synthesis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:670-0 [Conf]
  10. Ashok K. Murugavel, N. Ranganathan, Ramamurti Chandramouli, Srinath Chavali
    Average Power in Digital CMOS Circuits using Least Square Estimation. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:215-220 [Conf]
  11. Ashok K. Murugavel, N. Ranganathan, Ramamurti Chandramouli, Srinath Chavali
    Least-square estimation of average power in digital CMOS circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:1, pp:55-58 [Journal]
  12. Ashok K. Murugavel, N. Ranganathan
    A game theoretic approach for power optimization during behavioral synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:6, pp:1031-1043 [Journal]
  13. Ashok K. Murugavel, N. Ranganathan
    Petri net modeling of gate and interconnect delays for power estimation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:5, pp:921-927 [Journal]

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