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Publications of Author

1. Maher N. Mneimneh, Karem A. Sakallah, John Moondanos
   Preserving synchronizing sequences of sequential circuits after retiming. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2004, pp:579-584 [Conf]
   
2. Sung-Jui (Song-Ra) Pan, Kwang-Ting Cheng, John Moondanos, Ziyad Hanna
   Generation of shorter sequences for high resolution error diagnosis using sequential SAT. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2006, pp:25-29 [Conf]
   
3. John Moondanos, Carl-Johan H. Seger, Ziyad Hanna, Daher Kaiss
   CLEVER: Divide and Conquer Combinational Logic Equivalence VERification with False Negative Elimination. [Citation Graph (0, 0)][DBLP]
   CAV, 2001, pp:131-143 [Conf]
   
4. Feng Lu, Li-C. Wang, Kwang-Ting Cheng, John Moondanos, Ziyad Hanna
   A signal correlation guided ATPG solver and its applications for solving difficult industrial cases. [Citation Graph (0, 0)][DBLP]
   DAC, 2003, pp:436-441 [Conf]
   
5. Abhijit Davare, Qi Zhu, John Moondanos, Alberto L. Sangiovanni-Vincentelli
   JPEG Encoding on the Intel MXP5800: A Platform-Based Design Case Study. [Citation Graph (0, 0)][DBLP]
   ESTImedia, 2005, pp:89-94 [Conf]
   
6. John Moondanos, Jacob A. Abraham
   Sequential Redundancy Identification Using Verification Techniques. [Citation Graph (0, 0)][DBLP]
   ITC, 1992, pp:197-205 [Conf]
   
7. Yatin Vasant Hoskote, John Moondanos, Jacob A. Abraham, Donald S. Fussell
   Verification of Circuits Described in VHDL through Extraction of Design Intent. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 1994, pp:417-420 [Conf]
   
8. John Moondanos
   From Error to Error: Logic Debugging in the Many-Core Era. [Citation Graph (0, 0)][DBLP]
   Electr. Notes Theor. Comput. Sci., 2007, v:174, n:4, pp:3-7 [Journal]
   
9. Feng Lu, Li-C. Wang, Kwang-Ting (Tim) Cheng, John Moondanos, Ziyad Hanna
   A Signal Correlation Guided Circuit-SAT Solver. [Citation Graph (0, 0)][DBLP]
   J. UCS, 2004, v:10, n:12, pp:1629-1654 [Journal]
   
10. Yatin Vasant Hoskote, Jacob A. Abraham, Donald S. Fussell, John Moondanos
    Automatic verification of implementations of large circuits against HDL specifications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:3, pp:217-228 [Journal]