The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Sang Lyul Min: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Jongmoo Choi, Sam H. Noh, Sang Lyul Min, Yookun Cho
    An Adaptive Block Management Scheme Using On-Line Detection of Block Reference Patterns. [Citation Graph (1, 0)][DBLP]
    IW-MMDBMS, 1998, pp:172-179 [Conf]
  2. Sang Lyul Min, Eyee Hyun Nam
    Current trends in flash memory technology: invited paper. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2006, pp:332-333 [Conf]
  3. Sang Lyul Min, Jong-Deok Choi
    An Efficient Cache-Based Access Anomaly Detection Scheme. [Citation Graph (0, 0)][DBLP]
    ASPLOS, 1991, pp:235-244 [Conf]
  4. Bernhard Egger, Chihun Kim, Choonki Jang, Yoonsung Nam, Jaejin Lee, Sang Lyul Min
    A dynamic code placement technique for scratchpad memory using postpass optimization. [Citation Graph (0, 0)][DBLP]
    CASES, 2006, pp:223-233 [Conf]
  5. Sang Lyul Min, Yarsun Hsu, Hyoung-Joo Kim
    A Design of Performance-optimized Control-based Synchronization. [Citation Graph (0, 0)][DBLP]
    CONPAR, 1990, pp:312-323 [Conf]
  6. Woonseok Kim, Jihong Kim, Sang Lyul Min
    A Dynamic Voltage Scaling Algorithm for Dynamic-Priority Hard Real-Time Systems Using Slack Time Analysis. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:788-794 [Conf]
  7. Kanghee Kim, Lucia Lo Bello, Sang Lyul Min, Orazio Mirabella
    On Relaxing Task Isolation in Overrun Handling to Provide Probabilistic Guarantees to Soft Real-Time Tasks with Varying Execution Times. [Citation Graph (0, 0)][DBLP]
    ECRTS, 2002, pp:193-202 [Conf]
  8. Chanik Park, Junghee Lim, Kiwon Kwon, Jaejin Lee, Sang Lyul Min
    Compiler-assisted demand paging for embedded systems with flash memory. [Citation Graph (0, 0)][DBLP]
    EMSOFT, 2004, pp:114-124 [Conf]
  9. Jesung Kim, Sang Lyul Min, Sanghoon Jeon, Byoungchul Ahn, Deog-Kyoon Jeong, Chong-Sang Kim
    U-Cache: A Cost-Effective Solution to the Synonym Problem. [Citation Graph (0, 0)][DBLP]
    HPCA, 1995, pp:243-252 [Conf]
  10. Yujin Lim, Jesung Kim, Sang Lyul Min, Joong Soo Ma
    Performance Evaluation of the Bluetooth-Based Public Internet Access Point. [Citation Graph (0, 0)][DBLP]
    ICOIN, 2001, pp:643-648 [Conf]
  11. Sang Lyul Min, Jean-Loup Baer
    A Timestamp-based Cache Coherence Scheme. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1989, pp:23-32 [Conf]
  12. Sang Lyul Min, Jean-Loup Baer
    A Performance Comparison of Directory-based and Timestamp-based Cache Coherence Schemes. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1990, pp:305-311 [Conf]
  13. Sang Lyul Min, Jean-Loup Baer, Hyoung-Joo Kim
    An efficient caching support for critical sections in large-scale shared-memory multiprocessors. [Citation Graph (0, 0)][DBLP]
    ICS, 1990, pp:34-47 [Conf]
  14. Woonseok Kim, Jihong Kim, Sang Lyul Min
    Dynamic voltage scaling algorithm for fixed-priority real-time systems using work-demand analysis. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2003, pp:396-401 [Conf]
  15. Woonseok Kim, Jihong Kim, Sang Lyul Min
    Preemption-aware dynamic voltage scaling in hard real-time systems. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:393-398 [Conf]
  16. Jinhyuk Yoon, Sang Lyul Min, Yookun Cho
    Buffer Cache Management: Predicting the Future from the Past. [Citation Graph (0, 0)][DBLP]
    ISPAN, 2002, pp:105-110 [Conf]
  17. Sheayun Lee, Andreas Ermedahl, Sang Lyul Min, Naehyuck Chang
    An Accurate Instruction-Level Energy Consumption Model for Embedded RISC Processors. [Citation Graph (0, 0)][DBLP]
    LCTES/OM, 2001, pp:1-10 [Conf]
  18. Sheayun Lee, Chang-Gun Lee, Minsuk Lee, Sang Lyul Min, Chong-Sang Kim
    Limited Preemptible Scheduling to Embrace Cache Memory in Real-Time Systems. [Citation Graph (0, 0)][DBLP]
    LCTES, 1998, pp:51-64 [Conf]
  19. Jong Min Kim, Jongmoo Choi, Jesung Kim, Sam H. Noh, Sang Lyul Min, Yookun Cho, Chong-Sang Kim
    A Low-Overhead, High-Performance Unified Buffer Management Scheme That Exploits Sequential and Looping References. [Citation Graph (0, 0)][DBLP]
    OSDI, 2000, pp:119-134 [Conf]
  20. Dongkun Shin, Woonseok Kim, Jaekwon Jeon, Jihong Kim, Sang Lyul Min
    SimDVS: An Integrated Simulation Environment for Performance Evaluation of Dynamic Voltage Scaling Algorithms. [Citation Graph (0, 0)][DBLP]
    PACS, 2002, pp:141-156 [Conf]
  21. Jong-Deok Choi, Sang Lyul Min
    Race Frontier: Reproducing Data Races in Parallel-Program Debugging. [Citation Graph (0, 0)][DBLP]
    PPOPP, 1991, pp:145-154 [Conf]
  22. Sung-Kwan Kim, Sang Lyul Min, Rhan Ha
    Efficient worst case timing analysis of data caching. [Citation Graph (0, 0)][DBLP]
    IEEE Real Time Technology and Applications Symposium, 1996, pp:230-240 [Conf]
  23. Woonseok Kim, Dongkun Shin, Han-Saem Yun, Jihong Kim, Sang Lyul Min
    Performance Comparison of Dynamic Voltage Scaling Algorithms for Hard Real-Time Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Real Time Technology and Applications Symposium, 2002, pp:219-228 [Conf]
  24. Hyosoon Lee, Heonshik Shin, Sang Lyul Min
    Worst Case Timing Requirement of Real-Time Tasks with Time Redundancy. [Citation Graph (0, 0)][DBLP]
    RTCSA, 1999, pp:410-0 [Conf]
  25. Sung-Soo Lim, Jihong Kim, Sang Lyul Min
    A Worst Case Timing Analysis Technique for Optimized Programs. [Citation Graph (0, 0)][DBLP]
    RTCSA, 1998, pp:151-157 [Conf]
  26. Chang-Gun Lee, Young-Kuk Kim, Sang Hyuk Son, Sang Lyul Min, Chong-Sang Kim
    Efficiently supporting hard/soft deadline transactions in real-time database systems. [Citation Graph (0, 0)][DBLP]
    RTCSA, 1996, pp:74-80 [Conf]
  27. José Luis Díaz, Daniel F. García, Kanghee Kim, Chang-Gun Lee, Lucia Lo Bello, José María López, Sang Lyul Min, Orazio Mirabella
    Stochastic Analysis of Periodic Real-Time Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Real-Time Systems Symposium, 2002, pp:289-0 [Conf]
  28. Yerang Hur, Young Hyun Bae, Sung-Soo Lim, Sung-Kwan Kim, Byung-Do Rhee, Sang Lyul Min, Chang Yun Park, Heonshik Shin, Chong-Sang Kim
    Worst Case Timing Analysis of RISC Processors: R3000/R3010 Case Study. [Citation Graph (0, 0)][DBLP]
    IEEE Real-Time Systems Symposium, 1995, pp:308-321 [Conf]
  29. Sung-Kwan Kim, Sang Lyul Min, Rhan Ha
    Analysis of the Impacts of Overestimation Sources on the Accuracy of Worst Case Timing Analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Real-Time Systems Symposium, 1999, pp:22-31 [Conf]
  30. Chang-Gun Lee, Joosun Hahn, Sang Lyul Min, Rhan Ha, Seongsoo Hong, Chang Yun Park, Minsuk Lee, Chong-Sang Kim
    Analysis of cache-related preemption delay in fixed-priority preemptive scheduling. [Citation Graph (0, 0)][DBLP]
    IEEE Real-Time Systems Symposium, 1996, pp:264-274 [Conf]
  31. Chang-Gun Lee, Joosun Hahn, Yang-Min Seo, Sang Lyul Min, Rhan Ha, Seongsoo Hong, Chang Yun Park, Minsuk Lee, Chong-Sang Kim
    Enhanced analysis of cache-related preemption delay in fixed-priority preemptive scheduling. [Citation Graph (0, 0)][DBLP]
    IEEE Real-Time Systems Symposium, 1997, pp:187-198 [Conf]
  32. Minsuk Lee, Sang Lyul Min, Chang Yun Park, Young Hyun Bae, Heonshik Shin, Chong-Sang Kim
    A Dual-Mode Instruction Prefetch Scheme for Improved Worst Case and Average Case Program Execution Times. [Citation Graph (0, 0)][DBLP]
    IEEE Real-Time Systems Symposium, 1993, pp:98-105 [Conf]
  33. Sung-Soo Lim, Young Hyun Bae, Gyu Tae Jang, Byung-Do Rhee, Sang Lyul Min, Chang Yun Park, Heonshik Shin, Kunsoo Park, Chong-Sang Kim
    An Accurate Worst Case Timing Analysis Technique for RISC Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Real-Time Systems Symposium, 1994, pp:142-151 [Conf]
  34. Sung-Soo Lim, Jung Hee Han, Jihong Kim, Sang Lyul Min
    A Worst Case Timing Analysis Technique for Multiple-Issue Machines. [Citation Graph (0, 0)][DBLP]
    IEEE Real-Time Systems Symposium, 1998, pp:334-345 [Conf]
  35. Insik Shin, Insup Lee, Sang Lyul Min
    Embedded System Design Framework for Minimizing Code Size and Guaranteeing Real-Time Requirements. [Citation Graph (0, 0)][DBLP]
    IEEE Real-Time Systems Symposium, 2002, pp:201-211 [Conf]
  36. Sung-Kwan Kim, Jongmoo Choi, Donghee Lee, Sam H. Noh, Sang Lyul Min
    Virtual framework for testing the reliability of system software on embedded systems. [Citation Graph (0, 0)][DBLP]
    SAC, 2007, pp:1192-1196 [Conf]
  37. Sheayun Lee, Jaejin Lee, Sang Lyul Min, Jason Hiser, Jack W. Davidson
    Code Generation for a Dual Instruction Set Processor Based on Selective Code Transformation. [Citation Graph (0, 0)][DBLP]
    SCOPES, 2003, pp:33-48 [Conf]
  38. Sheayun Lee, Jaejin Lee, Chang Yun Park, Sang Lyul Min
    A Flexible Tradeoff Between Code Size and WCET Using a Dual Instruction Set Processor. [Citation Graph (0, 0)][DBLP]
    SCOPES, 2004, pp:244-258 [Conf]
  39. Jongmoo Choi, Sam H. Noh, Sang Lyul Min, Yookun Cho
    Towards application/file-level characterization of block references: a case for fine-grained buffer management. [Citation Graph (0, 0)][DBLP]
    SIGMETRICS, 2000, pp:286-295 [Conf]
  40. Donghee Lee, Jongmoo Choi, Jong-Hun Kim, Sam H. Noh, Sang Lyul Min, Yookun Cho, Chong-Sang Kim
    On the Existence of a Spectrum of Policies that Subsumes the Least Recently Used (LRU) and Least Frequently Used (LFU) Policies. [Citation Graph (0, 0)][DBLP]
    SIGMETRICS, 1999, pp:134-143 [Conf]
  41. Jongmoo Choi, Sam H. Noh, Sang Lyul Min, Yookun Cho
    An Implementation Study of a Detection-Based Adaptive Block Replacement Scheme. [Citation Graph (0, 0)][DBLP]
    USENIX Annual Technical Conference, General Track, 1999, pp:239-252 [Conf]
  42. Hyokyung Bahn, Sam H. Noh, Sang Lyul Min, Kern Koh
    Using Full Reference History for Efficient Document Replacement in Web Caches. [Citation Graph (0, 0)][DBLP]
    USENIX Symposium on Internet Technologies and Systems, 1999, pp:- [Conf]
  43. Sheayun Lee, Jaejin Lee, Chang Yun Park, Sang Lyul Min
    A Flexible Tradeoff between Code Size and WCET Employing Dual Instruction Set Processors. [Citation Graph (0, 0)][DBLP]
    WCET, 2003, pp:91-94 [Conf]
  44. Hyokyung Bahn, Hyunsook Lee, Sam H. Noh, Sang Lyul Min, Kern Koh
    Replica-aware caching for Web proxies. [Citation Graph (0, 0)][DBLP]
    Computer Communications, 2002, v:25, n:3, pp:183-188 [Journal]
  45. Hyokyung Bahn, Kern Koh, Sang Lyul Min, Sam H. Noh
    Efficient Replacement of Nonuniform Objects in Web Caches. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2002, v:35, n:6, pp:65-73 [Journal]
  46. Jong Min Kim, Donghee Lee, Sam H. Noh, Sang Lyul Min, Yookun Cho, Chong-Sang Kim
    An accurate and practical buffer allocation model for the buffer cache based on marginal gains. [Citation Graph (0, 0)][DBLP]
    Inf. Process. Lett., 2003, v:85, n:2, pp:93-97 [Journal]
  47. Kunsoo Park, Sang Lyul Min, Yookun Cho
    The Working Set Algorithm has Competitive Ratio Less Than Two. [Citation Graph (0, 0)][DBLP]
    Inf. Process. Lett., 1997, v:63, n:4, pp:183-188 [Journal]
  48. Joosun Hahn, Rhan Ha, Sang Lyul Min, Jane W.-S. Liu
    Analysis of Worst Case DMA Response Time in a Fixed-Priority Bus Arbitration Protocol. [Citation Graph (0, 0)][DBLP]
    Real-Time Systems, 2002, v:23, n:3, pp:209-238 [Journal]
  49. Sheayun Lee, Sang Lyul Min, Chong-Sang Kim, Chang-Gun Lee, Minsuk Lee
    Cache-Conscious Limited Preemptive Scheduling. [Citation Graph (0, 0)][DBLP]
    Real-Time Systems, 1999, v:17, n:2-3, pp:257-282 [Journal]
  50. Minsuk Lee, Sang Lyul Min, Heonshik Shin, Chong-Sang Kim, Chang Yun Park
    Threaded Prefetching: A New Instruction Memory Hierarchy for Real-Time Systems. [Citation Graph (0, 0)][DBLP]
    Real-Time Systems, 1997, v:13, n:1, pp:47-65 [Journal]
  51. Jongmoo Choi, Sam H. Noh, Sang Lyul Min, Eun-Yong Ha, Yookun Cho
    Design, Implementation, and Performance Evaluation of a Detection-Based Adaptive Block Replacement Scheme. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2002, v:51, n:7, pp:793-800 [Journal]
  52. Kanghee Kim, José Luis Díaz, Lucia Lo Bello, José María López, Chang-Gun Lee, Sang Lyul Min
    An Exact Stochastic Analysis of Priority-Driven Periodic Real-Time Systems and Its Approximations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2005, v:54, n:11, pp:1460-1466 [Journal]
  53. Chang-Gun Lee, Joosun Hahn, Yang-Min Seo, Sang Lyul Min, Rhan Ha, Seongsoo Hong, Chang Yun Park, Minsuk Lee, Chong-Sang Kim
    Analysis of Cache-Related Preemption Delay in Fixed-Priority Preemtive Scheduling. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1998, v:47, n:6, pp:700-713 [Journal]
  54. Donghee Lee, Jongmoo Choi, Jong-Hun Kim, Sam H. Noh, Sang Lyul Min, Yookun Cho, Chong-Sang Kim
    LRFU: A Spectrum of Policies that Subsumes the Least Recently Used and Least Frequently Used Policies. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2001, v:50, n:12, pp:1352-1361 [Journal]
  55. Sang Lyul Min, Jean-Loup Baer
    Design and Analysis of a Scalable Cache Coherence Scheme Based on Clocks and Timestamps. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1992, v:3, n:1, pp:25-44 [Journal]
  56. Chang-Gun Lee, Kwangpo Lee, Joosun Hahn, Yang-Min Seo, Sang Lyul Min, Rhan Ha, Seongsoo Hong, Chang Yun Park, Minsuk Lee, Chong-Sang Kim
    Bounding Cache-Related Preemption Delay for Real-Time Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Software Eng., 2001, v:27, n:9, pp:805-826 [Journal]
  57. Sung-Soo Lim, Young Hyun Bae, Gyu Tae Jang, Byung-Do Rhee, Sang Lyul Min, Chang Yun Park, Heonshik Shin, Kunsoo Park, Soo-Mook Moon, Chong-Sang Kim
    An Accurate Worst Case Timing Analysis for RISC Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Software Eng., 1995, v:21, n:7, pp:593-604 [Journal]
  58. Sang Lyul Min, Eyee Hyun Nam, Young Hee Lee
    Evolution of NAND Flash Memory Interface. [Citation Graph (0, 0)][DBLP]
    Asia-Pacific Computer Systems Architecture Conference, 2007, pp:75-79 [Conf]
  59. Seongjun Ahn, Jongmoo Choi, Donghee Lee, Sam H. Noh, Sang Lyul Min, Yookun Cho
    Design, Implementation, and Performance Evaluation of Flash Memory-based File System on Chip. [Citation Graph (0, 0)][DBLP]
    J. Inf. Sci. Eng., 2007, v:23, n:6, pp:1865-1887 [Journal]
  60. Sheayun Lee, Jaejin Lee, Chang Yun Park, Sang Lyul Min
    Selective code transformation for dual instruction set processors. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Embedded Comput. Syst., 2007, v:6, n:2, pp:- [Journal]
  61. Woonseok Kim, Dongkun Shin, Han-Saem Yun, Jihong Kim, Sang Lyul Min
    Performance Evaluation of Dynamic Voltage Scaling Algorithms for Hard Real-Time Systems. [Citation Graph (0, 0)][DBLP]
    J. Low Power Electronics, 2005, v:1, n:3, pp:207-216 [Journal]

  62. LTFTL: lightweight time-shift flash translation layer for flash memory based embedded storage. [Citation Graph (, )][DBLP]


  63. Development Platforms for Flash Memory Solid State Disks. [Citation Graph (, )][DBLP]


  64. Flash memory-based storage device for mobile embedded applications. [Citation Graph (, )][DBLP]


Search in 0.006secs, Finished in 0.009secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002