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Publications of Author

1. Jacob R. Minz, Sung Kyu Lim
   Layer assignment for reliable system-on-package. [Citation Graph (0, 0)][DBLP]
   ASP-DAC, 2004, pp:31-37 [Conf]
   
2. Mongkol Ekpanyapong, Jacob R. Minz, Thaisiri Watewai, Hsien-Hsin S. Lee, Sung Kyu Lim
   Profile-guided microarchitectural floorplanning for deep submicron processor design. [Citation Graph (0, 0)][DBLP]
   DAC, 2004, pp:634-639 [Conf]
   
3. Jacob R. Minz, Mohit Pathak, Sung Kyu Lim
   Net and Pin Distribution for 3D Package Global Routing. [Citation Graph (0, 0)][DBLP]
   DATE, 2004, pp:1410-1411 [Conf]
   
4. Jacob R. Minz, Somaskanda Thyagaraja, Sung Kyu Lim
   Optical routing for 3D system-on-package. [Citation Graph (0, 0)][DBLP]
   DATE, 2006, pp:337-338 [Conf]
   
5. Jacob R. Minz, Sung Kyu Lim, Cheng-Kok Koh
   3D module placement for congestion and power noise reduction. [Citation Graph (0, 0)][DBLP]
   ACM Great Lakes Symposium on VLSI, 2005, pp:458-461 [Conf]
   
6. Eric Wong, Jacob R. Minz, Sung Kyu Lim
   Decoupling capacitor planning and sizing for noise and leakage reduction. [Citation Graph (0, 0)][DBLP]
   ICCAD, 2006, pp:395-400 [Conf]
   
7. Mongkol Ekpanyapong, Jacob R. Minz, Thaisiri Watewai, Hsien-Hsin S. Lee, Sung Kyu Lim
   Profile-guided microarchitectural floor planning for deep submicron processor design. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:7, pp:1289-1300 [Journal]
   
8. Jacob R. Minz, Sung Kyu Lim
   Block-level 3-D Global Routing With an Application to 3-D Packaging. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:10, pp:2248-2257 [Journal]
   
9. Eric Wong, Jacob R. Minz, Sung Kyu Lim
   Multi-Objective Module Placement For 3-D System-On-Package. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2006, v:14, n:5, pp:553-557 [Journal]
   
10. 
    Buffered clock tree synthesis for 3D ICs under thermal variations. [Citation Graph (, )][DBLP]